High speed link control protocol transmission processing/module and data processing/method

Abstract

This invention relates to HDLC protocol transmission process module including a port arbitration module, a HDLC protocol transmission processor and a state memory module. The data process method is that the port arbitration module receives data request signals of N ports and transfers them to the HDLC protocol processor orderly according to the priorities and provides arbitration to the shared data process pipelines of N ports, the HDLC processor reads out unprocessed data from FIFO and reads out the state data of its belonged HDLC channel from the state memory module be processed wit hpipelines to be sent to related ports to write back to the state memory the new state data of HDLC channel.

Description

technical field [0001] The invention belongs to the technical field of network interconnection equipment, and in particular relates to the structural design of a high-speed data link control (HDLC) protocol transmission processing module and a data processing method thereof. Background technique [0002] Serial communication control chips are usually used in communication devices such as routers and switches, and often need to control multi-port and multi-channel data streams at the same time, which means performing high-speed data links on multiple channels of multiple ports at the same time. Send / receive processing of the HDLC protocol. [0003] The HDLC protocol is at the second layer of the Open Systems Interconnection (OSI) seven-layer network reference model: the data link layer. The data frame structure of the HDLC protocol is shown in Figure 1. In the figure: the HDLC data frame uses the hexadecimal number 7E (0x7E) as the frame start and frame end signs, and there ...

AI Technical Summary

Problems solved by technology

The arbitration in these places becomes the bottleneck of the system speed, so even if the speed of each processor is increased, the port rate cannot be effectively improved

Using this scheme, when the main clock is 33MHz, the maximum port rate of each port can only reach about 8Mbps at most, and since 16 sending HDLC protocol processors are used, the occupied chip area is also large

Images