Cache system and cache memory control device controlling cache memory having two access modes
A technology of cache and control unit, applied in the direction of memory system, machine execution device, memory architecture access/allocation, etc.
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no. 1 example
[0035] (structure)
[0036] The cache memory 100 shown in FIG. 1 is configured in a two-way set associative manner. Referring to the figure, a cache 100 includes a tag memory 1 , comparators 920 , 921 , a miss determination unit 3 , a cache access mode switching unit 9 , a data memory 4 , a latch circuit 6 and a selector 5 .
[0037] Tag memory 1 is an address memory including two tag way 0 and tag way 1 as an address array. Stores tag addresses that associate tag path 0 and tag path 1 with index addresses.
[0038] The tag address specified by the index address of tag way 0 indicates the upper data address specified by the same index address of data way 0 described later. Similarly, the tag address specified by the index address of tag way 1 indicates the upper data address specified by the same index address of data way 1 .
[0039] Tag way 0 and tag way 1 input an index address which is a lower address of the designated address, and output a tag address corresponding to ...
no. 2 example
[0105] A cache system 300 shown in FIG. 9 includes a cache 100 , a CPU 130 , an instruction queue 18 , a queue control unit 31 , and a branch prefetch determination unit 19 . The cache system of this embodiment has common parts with the cache system of the first embodiment shown in FIG. 5 . Among the constituent elements in FIG. 9 , the same constituent elements as in FIG. 5 are assigned the same numerals as in FIG. 5 . The following is just an explanation of the different parts.
[0106] After the CPU 130 executes the branch instruction, it outputs a branch request signal to the branch prefetch determination unit 19 and the queue control unit 31 , and outputs a branch destination address signal to the branch prefetch determination unit 19 .
[0107] When the branch prefetch determination section 19 does not receive any one of the branch request signal or the prefetch request signal, the flag enable signal is set to "L" level, and the cache access mode switching signal is set...
no. 3 example
[0122] Cache system 400 shown in FIG. 12 includes instruction cache 98 , data cache 99 , CPU 140 , and register number match determination unit 21 . The cache system of this embodiment has common parts with the cache system of the first embodiment shown in FIG. 5 . Among the constituent elements in FIG. 12 , the same constituent elements as in FIG. 5 are given the same reference numerals as those in FIG. 5 . Only the different parts are described below.
[0123] In this embodiment, the cache is divided into an instruction cache 98 storing instructions and a data cache 99 storing data.
[0124]When decoding an instruction in the DEC stage, if the instruction is a load instruction storing data in a register, CPU 140 outputs a storage register number signal indicating the register number included in the instruction to register number match determination unit 21 .
[0125] When the instruction after the load instruction (not limited to immediately following it) is decoded in the...
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