Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device capable of suitably suppressing the increase of resistance while maintaining the performance of a transistor at a required level, and to provide a method for manufacturing the semiconductor device. In a p-well 30, grooves 34, 35 are formed between the source area 31 and a channel 33 or between the drain area 32 and the channel 33 of a p-channel high voltage resistance transistor UNT, and the insides of the grooves 34, 35 are respectively filled with insulating substances 34z, 35z. In the p-well 30, an LDD area 36 whose impurity concentration is smaller than that of the source area 31 is formed from the channel 33 side to the source area 31 side along the groove 34. In the p-well, an LDD area 37 whose impurity concentration is smaller than that of the drain area 32 is formed from the channel 33 side to the drain area 32 side along the groove 35.

Description

technical field [0001] The present invention relates to a semiconductor device having an LDD (Lightly Doped Drain) region (low-concentration doped drain) and a manufacturing method thereof. Background technique [0002] In recent years, there has been an increasing demand for high integration of semiconductor devices. Under such circumstances, there is an increasing demand to form a plurality of transistors having different withstand voltage characteristics on the same semiconductor substrate. Forming a plurality of transistors having such different withstand voltage characteristics on the same semiconductor substrate can be performed by adjusting the gate length and the implantation concentration of impurities into the source region and the drain region for each transistor. [0003] However, if a transistor is formed by such adjustment, it is easy to increase the element size. For example, after forming a high withstand voltage transistor, when it is necessary to form the...

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Problems solved by technology

[0004] In this way, when forming transistors with various withstand voltage characteristics on the same semiconductor substrate, since the element size of high withstand voltage transistors is likely to increase, it will become difficult to meet the miniaturization requirements of semiconductor devices.

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