Computer micro system structure comprising explicit high-speed buffer storage

Abstract

The architecture comprises memory, cache, registers and arithmetical unit, as well as comprises Ecache inside CPU chip. The said Ecache and memory are coded unitedly. Since Ecache is inside CPU. Thus, it is guaranteed that hardware accesses Ecache rapidly. United coded addresses are started from small address. Thus, in all command of accessing memories, addresses of accessing Ecache is visible, and is easy for hardware to recognize and realize. Several groups of commands are designed to support compiler and running routine to use Ecache in explicit and manage Ecache dynamically. These commands and Ecache are indiscerptible integration.

Description

technical field [0001] The present invention relates to computer systems, and in particular to computer microarchitectures containing explicit cache memory (abbreviated as Ecache). technical background [0002] In the past 50 years, computer performance has generally increased according to Moore's law, mainly relying on the technology of increasing the operating frequency of the machine and using various parallel mechanisms. Although storage technology has also developed, there is still a large gap between memory speed and processor speed. Modern computers have a level-1, level-2, or even level-3 cache memory (Cache) between memory and registers. It is hoped that the data in the cache can be reused to alleviate the contradiction of slow memory access (see Figure 1). [0003] Why can adding Cache in the chip alleviate memory access conflicts? Let's take the process of CPU reading data as an example to briefly explain the working process of Cache (see Figure 3 for the workin...

AI Technical Summary

Problems solved by technology

Memory access misses the Cache is the main cause of delay;

[0012] 3) The Cache structure is invisible to the compiler and knows its existence, but it cannot purposefully allocate data with good reusabi

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