Device test apparatus and test method

Abstract

One test board for executing a test is provided for each of a plurality of DUTs (Devices-Under-Test) such as semiconductor integrated circuits, a multi test board controller for managing these test boards is provided, and a plurality of test boards managed by each multi test board controller are operated in parallel to simultaneously perform independent tests on the respective DUTs.

Description

technical field [0001] The present invention relates to a kind of equipment and method for testing devices under test, such as semiconductor integrated circuits such as large scale integration (LSI) wafers, and more particularly to a testing device and a testing method capable of performing independent tests on many devices under test at the same time . Background technique [0002] Conventionally, multiple devices under test are independently tested simultaneously (for example, Japanese Utility Model Application Laid-Open No. 64-47148 / 1989). figure 1 is a block diagram of a conventional test device disclosed in Japanese Utility Model Application Laid-Open No. 64-47148 / 1989. The test equipment includes: a plurality of test units 31-33 controlled by a microprocessor that has stored a test program that operates independently; processing with a monitoring function and a human-machine interface function for monitoring the operating conditions of each test unit 31-33 processor ...

AI Technical Summary

Problems solved by technology

Also, the transmission time of the test results obtained in each test unit and the waiting time until the test results are transmitted increase due to the influence of the communication time and the increase of the processing time.

As a result, there is a problem of reduced test efficiency, which affects mass production

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