Magnetic memory device and magnetic substrate
A magnetic storage and memory cell technology, applied in information storage, static memory, digital memory information, etc., can solve problems such as high power consumption, and achieve the effects of reducing power consumption, reducing leakage current, and reducing load capacitance
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Embodiment 1
[0183]
[0184] The MRAM of Embodiment 1 of the present invention is characterized in that: the easy magnetization axis of the soft ferromagnetic layer constituting the MRAM cell is not parallel to the bit line and the word line. ~50 degree angle.
[0185]
[0186]
[0187] First, use figure 1 A representative structure of an MRAM cell will be described. figure 1 The illustrated MRAM cell MC has a pn junction diode 7 formed by laminating an n + silicon layer 10 and a p + silicon layer 11 .
[0188] Afterwards, a tungsten terminal 12 is disposed on the top of the pn junction diode 7 , and the pn junction diode 7 is electrically connected to a magnetic tunnel junction (Magnetic Tunnel Junction: MTJ) 8 via the tungsten terminal 12 .
[0189] The MTJ8 has a laminated structure, and the template layer 15 (thickness: 10nm) made of platinum (Pt), Ni 81 Fe 19 The initial ferromagnetic layer 16 (thickness 4nm) made of Permalloy, Mn 54 Fe 46 The antiferromagnetic layer 18 ...
example 2
[0351] As a modification 2 of Embodiment 2 of the present invention, Figure 33 Indicates MRAM300. The MRAM300 is featured with the Figure 31 The illustrated MRAM 200 has almost the same structure, except that the PMOS transistor MP11 and the NMOS transistor MN12, the PMOS transistor MP13 and the NMOS transistor MN14, the PMOS transistor MP21 and the NMOS transistor MN22, and the PMOS transistor MP23 and the NMOS transistor MN24 are inserted between the respective drain electrodes. NMOS transistors MN15 , MN16 , MN25 and MN26 and NMOS transistors QN1 and QN2 are interposed between the drain electrodes of the PMOS transistor QP11 and NMOS transistor QN12 , the PMOS transistor QP21 and NMOS transistor QN22 .
[0352] The gate voltages of the NMOS transistors MN15, MN16, MN25, MN26, QN1 and QN2 are fixed to the DC voltage V GG .
[0353] The purpose of these NMOS transistors is to reduce leakage current. That is, the cause of the leakage current of the MOSFET is BTBT (Band t...
Embodiment 3
[0362]
[0363] The MRAM according to Embodiment 3 of the present invention is characterized in that word lines or bit lines of the MRAM cell array are divided into a plurality of sub-word lines and sub-bit lines.
[0364] That is, when the resistivity of the wiring is p, the wiring length is 1, and the cross-sectional area of the wiring is S, the wiring resistance R is given by the following equation (9).
[0365] [Formula 9]
[0366] R = ρ l ρ · · · · · · · · ( 9 )
[0367] When the current flowing through the wiring is I, the power consumption P is given by the following equation (10).
[0368] [Formula 10]
[0369] P = RI 2 = ρ ll 2 ...
PUM
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