Variable latency stack cache and method for providing data

A memory and data technology, applied in static memory, memory system, digital memory information, etc., can solve the problems of short core clock cycle time, insufficient space, and reduced cache memory size.
CN1632877AActive Publication Date: 2005-06-29IP FIRST
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Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Applications(China)
Current Assignee / Owner
IP FIRST
Publication Date
2005-06-29

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Abstract

The present invention discloses a variable latency stack cache memory and a method for providing data. It includes a plurality of storage elements, and stores stack memory data in a last-in-first-out operation mode. This cache memory can distinguish between the request of fetch and download instructions, and operate by guessing that the fetch data may exist in the uppermost cache line of the cache memory; in addition, this cache memory will also store the stack data requested by the download instruction Make a guess and assume that its data will exist in the topmost cache rank of cache memory or in multiple cache ranks above it. Therefore, when the source virtual address of the download instruction hits the uppermost cache line of the cache memory, the speed of the cache memory to provide the download data will be faster than when the data is located in the lower cache line; or with a physical address Comes faster when comparing; or faster than when the data has to be provided from the microprocessor's off-stack cache memory.
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Description

[0001] Statement of priority

[0002] This case asserts that the United States claims priority based on an article entitled Microprocessor with Variable Latency Stack Cache (Microprocessor with Variable LatencyStack Cache), its application number is 10 / 759483 and its application date is 2004 January 16.

[0003] Related application documents

[0004] Application number Title 10 / 759559 Microprocessor and apparatus for performing fast Speculative pop operation from a stack memory 10 / 759564 Microprocessor and apparatus for performing speculative load operation from a stack memory 10 / 759489 Microprocessor and apparatus for performing fast pop operation from random access cache memory technical field

[0005] The present invention relates to a cache memory in a microprocessor, in particular to a cache memory capable of distinguishing stack and non-stack memory access. Background technique [0...

Claims

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