Method for generating a structure on a substrate

Abstract

Disclosed is a method for creating a structure(132)on a substrate (100), according to which a first oxide layer, a first nitride layer, and a second oxide layer are successively applied to the substrate (100) in a first step. A section of the second oxide layer and a section of the first nitride layer are then removed in order to expose a section of the first oxide layer. A portion of the first nitride layer, which is located on top of the first oxide layer and below the second oxide layer(112), is subsequently removed in order to define the area of the structure(132).

Description

Technical field [0001] The present invention is related to a method for producing a structure on a substrate, and is particularly related to a self-aligning method for producing a structure similar to, for example, a shortened gate oxide of a MOS transistor (Self-aligning) method. Background technique [0002] In some applications for the manufacture of semiconductors, it may be necessary to implement structures with smaller (shorter) dimensions, for example, in MOS transistors (MOS = metal oxide semiconductor), for example, in LDMOS transistors ( LDMOS = laterally diffused metal oxide semiconductor, gate electrode, or gate oxide, among them. [0003] In the prior art, lithography methods are known, and (multi) gate electrodes can be manufactured by using these lithography methods, and since these known methods are not self-aligned, Therefore, it will cause restrictions based on the limited alignment possibilities of the lighting equipment used. Furthermore, the gate structure ma...

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Problems solved by technology

[0003] In the state of the art, lithographic methods are known and (multiple) gate electrodes can be produced by using these lithographic methods, and since these known methods are not self-aligning, Consequently, a limitation based on the limited alignment possibilities of the used lighting equipment arises and, moreover, the resulting grid structure has the disadvantage that a certain grid length may not be achieved , and may not be able to achieve a specific tolerance

[0004] Furthermore, a further disadvantage of the known methods is that a different doping of the source region and the drain region, as it is required in, for example, an LDMOS transistor, or a DMOS transistor Similarly, the system is only difficultly possible, or, for short gate structures, it is not possible at all

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