flash memory

Abstract

The invention discloses a flash memory. It includes: a cylindrical main structure as a substrate, the main structure is an N-type silicon structure, including a middle part and two ends located on both sides of the middle part, and a gate is wrapped around the middle part to form a surrounding gate; The two end portions serve as source and drain electrodes and include a layer of P-type doped region; the portion of the end portion surrounded by the P-type doped region is led out through contact lines for applying substrate voltage. It can have a smaller gate length and use a cylindrical structure to enable the control gate and floating gate voltages to better control the channel, reduce the percentage of the total depletion region size occupied by the widening of the source and drain depletion regions, and suppress short channels. Channel effect, resist threshold voltage drift, and reduce flash memory read errors.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a flash memory. Background technique [0002] For NOR flash memory cells, the most important limit to the continued reduction in size is the shortening of the gate length. This is mainly because the channel thermal electron (CHE) injection compilation method requires a certain voltage at the drain terminal, and this voltage has a great influence on the penetration of the source and drain terminals. For short channel devices, the channel thermal electron (CHE) method Not applicable. Another problem is that this limits the programming rate of NOR flash compared to NAND and AND data storage devices. According to the prediction of the document "G. Servalli, et al., IEDMTech. Dig., 35_1, 2005", the physical limit of the gate length reduction of the traditional flash memory structure is 130nm. [0003] Existing flash memory storage units generally use polysilicon as the float...

AI Technical Summary

Problems solved by technology

There are inherent defects in the flash memory technology of floating gate transistors. The thin dielectric layer below 100 nanometers will cause leakage, which will lead to data interference and chip failure results.

In addition, devices below the sub-100nm technology node will have a more serious short channel effect (Short Channel Effect), which affects the electrical characteristics of the storage device, making its threshold voltage drift compared with the long channel, resulting in possible readout errors

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