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A kind of Sonos flash memory device and compiling method thereof

A flash memory device and substrate technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of high current consumption, low efficiency of channel hot electron injection, and high voltage, so as to increase cell density, Effect of suppressing short channel effect and reducing readout errors

Active Publication Date: 2017-06-23
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the structure of the flash memory device disclosed in the above-mentioned documents has the following problems: in order to ensure a high channel hot electron generation rate, a high voltage must be applied to the drain terminal, and at the same time, in order to ensure a high hot electron injection efficiency, a high Voltage
Therefore, it is necessary to apply a high voltage to both the drain and the gate, which brings the problems of low channel hot electron injection efficiency and large current power consumption.

Method used

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  • A kind of Sonos flash memory device and compiling method thereof
  • A kind of Sonos flash memory device and compiling method thereof

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Embodiment 1

[0029] In this embodiment, the material of the first silicon gate 40 is polysilicon, its height is 90nm, and its length is 10nm; the material of the second silicon gate 50 is polysilicon, its height is 30nm, its length is 40nm; The material of the second oxide layer 80 is silicon dioxide with a thickness of 2 nm; the material of the third oxide layer 90 is silicon dioxide with a thickness of 8 nm. The manufacturing process of the device can be selected from the top-down technology compatible with the standard CMOS process.

[0030] In the SONOS flash memory device provided by the present invention, a cylindrical substrate structure is used, and the gate is covered on it. The use of a cylindrical structure can enable the voltage of the gate to better control the channel and suppress the short channel effect. , resist threshold voltage drift, reduce readout errors of flash memory, and at the same time, can effectively shorten the critical size of flash memory devices, increase t...

Embodiment 2

[0033] In this embodiment, when compiling the SONOS flash memory device, the voltage value applied to the first silicon gate 40 is equal to the threshold voltage value of the flash memory device, the voltage applied to the second silicon gate 50 is 8V, and the voltage applied to the drain terminal 30 is 4V. A voltage of 0V is applied to the source terminal 20 .

[0034] The compiling principle of the present invention is: when compiling a SONOS flash memory device, the voltage value applied to the first silicon gate 40 is equal to the threshold voltage value of the flash memory device, and a thinner channel electron layer is induced in the lower substrate region. The voltage applied to the second silicon gate 50 is greater than the threshold voltage of the flash memory device, and the voltage is coupled to the underlying silicon nitride layer 60 to induce a thicker channel electron layer in the lower channel electron layer. The voltage applied to the drain terminal 30 accelera...

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Abstract

The invention provides a SONOS flash memory device and a compiling method. The SONOS flash memory device includes a substrate in a cylindrical structure and a gate covering the middle part of the substrate; the ends on both sides of the substrate are respectively a source end and a drain end. , the gate includes a parallel first silicon gate and a second silicon gate, and a first oxide layer is provided between the first silicon gate and the second silicon gate; wherein, the second silicon gate and the substrate include in turn: A second oxide layer disposed on the substrate, a silicon nitride layer disposed on the second oxide layer for storing charges, and a third oxide layer disposed on the silicon nitride layer. The structure can suppress the short-channel effect, resist threshold voltage drift, and effectively shorten the critical size of the flash memory device. The programming method of the flash memory device in the present invention assists the movement of hot electrons by adjusting the voltage of the gate and the drain, provides enough energy to cross the oxide layer to complete the compilation, improves the compilation efficiency of the flash memory, and reduces the compilation current power consumption.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits and its manufacture, in particular to a SONOS flash memory device and its compiling method. Background technique [0002] With the miniaturization and miniaturization of semiconductor storage devices, the traditional polysilicon second silicon gate storage is difficult to adapt to the development requirements of future storage because of the excessive thickness of the stack and the high requirements on the insulation of the tunnel oxide layer. Recently, SONOS (Polysilicon-Oxide-Nitride-Oxide-Silicon, Silicon-Oxide-Nitride-Oxide-Silicon) non-volatile memory devices based on silicon nitride with excellent insulating properties are known as the first Two-silicon gate memory has stronger charge storage capacity, easy miniaturization and simple process, and has been re-emphasized. [0003] SONOS, the English acronym for Silicon-Oxide-Nitride-Oxide-Silicon, is a non-volatile memory that...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11563
Inventor 顾经纶
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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