Data reading method and device, memory and storage medium

A data reading and data technology, applied in the field of storage, can solve problems such as complex programming efficiency of programming algorithms, low reliability of memory storage, voltage fluctuations, etc., achieve strong compatibility, improve programming efficiency and reading efficiency, and reduce delay Effect

Active Publication Date: 2019-06-25
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the process of data writing, it is inevitable that voltage fluctuations will occur when voltage is applied to the gate, and this fluctuation will cause errors in the data stored in the memory cell when the voltage difference between two adjacent voltages is small ; resulting in problems such as low storage reliability of the memory
[0004] In the first pass technology, in order to reduce the above-mentioned storage error rate, the programming algorithm of the storage unit is used to increase the reliability, but this leads to problems such as complex programming algorithm and low programming efficiency.

Method used

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  • Data reading method and device, memory and storage medium
  • Data reading method and device, memory and storage medium
  • Data reading method and device, memory and storage medium

Examples

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example 1

[0134] Figure 7 Shown is a storage array of a 3D memory, the storage array includes a plurality of memory cells, the gates of the plurality of storage cells are connected to word lines (WL); the storage array also includes a serial selection transistor ( StringSelection Transistor, SST), the serial selection line (String Selection Line, SSL) to which the gate of the SST is connected. The storage array further includes: a ground selection transistor (Ground Selection Transistor, GST) located at the lowest end of the storage array for grounding; the gate of the GST is connected to a ground selection line (Ground Selection Line, GSL). Figure 7 It also shows a common source line (Common Source Line, CSL) of the storage array, and the CSL is connected to the source of the bottommost GST. When the memory array is in the working state, generally the SST and the GST are in the conduction state, so that the voltage injected from the drain of the transistor at the top can be conducte...

example 2

[0150] This example provides a data reading method, including:

[0151] According to the read address, the address bit is obtained;

[0152] Reading a status bit from a memory cell corresponding to the read address by using a threshold voltage;

[0153] The data to be read is obtained by combining the address bits and the status bits.

example 3

[0155] This example provides a data processing method, including:

[0156] A data programming step, the data programming step can be performed according to the data programming method provided in any of the foregoing embodiments;

[0157] The data reading step is located after the data programming step, and the specific implementation of the data reading step can be performed according to the data reading method provided in any of the foregoing embodiments.

[0158] This embodiment also provides a storage device, which may be any storage device described above, for example, a 2D storage device or a 3D storage device, and specifically a 3D NAND memory.

[0159] The storage devices may include:

[0160] memory;

[0161] A processor, connected to the memory, configured to implement the data programming method or the data reading method provided in any of the foregoing embodiments by executing computer-executable instructions on the memory.

[0162] The memory may include: 2D o...

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Abstract

The embodiment of the invention discloses a data reading method and device, a memory and a storage medium. The data programming method comprises the steps of obtaining a reading address of data reading; According to the read address, determining an address bit, wherein the address bit is composed of m bits, and m is a positive integer; reading the status bit from the second storage unit corresponding to the read address by using the read voltage corresponding to the N-m bits, Wherein the status bit is composed of N-m bits, the N is a positive integer greater than 2 and the m is a positive integer smaller than N; And combining the address bit and the state bit to obtain second data required to be read.

Description

technical field [0001] The present invention relates to the field of storage technology, in particular to a data reading method and device, a memory and a storage medium. Background technique [0002] Memory is a device that stores data. The memory includes a memory array; the memory array may be a two-dimensional (2D) memory array or a three-dimensional (3D) memory array. The storage array is composed of storage cells. The adjustable voltage of the threshold voltage storage unit is within a known voltage range. When writing data into the storage unit, usually a corresponding voltage is applied to the gate of the storage unit according to the need for data writing. When reading data from the storage unit, by adjusting the read voltage within the adjustable voltage range, combined with the conduction status of the storage unit, the data stored in the storage unit can be accurately read. [0003] In order to increase the storage capacity of the storage array, multi-value s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26G11C16/10G11C16/30
Inventor 赵成林刘红涛王明李达靳磊张念华霍宗亮
Owner YANGTZE MEMORY TECH CO LTD
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