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Method for implementing five-level tolerant flowing structure in integer unit of microprocessor

A pipeline structure and microprocessor technology, applied in the computer field, to achieve the effects of improving execution efficiency, improving error correction efficiency, and good fault tolerance

Inactive Publication Date: 2006-02-08
CHINA AEROSPACE TIMES ELECTRONICS CORP NO 771 RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, this method is only suitable for microprocessors with low performance requirements

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  • Method for implementing five-level tolerant flowing structure in integer unit of microprocessor
  • Method for implementing five-level tolerant flowing structure in integer unit of microprocessor
  • Method for implementing five-level tolerant flowing structure in integer unit of microprocessor

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Embodiment Construction

[0032] In the SPARC V8 compatible microprocessor LSFT32, a five-level fault-tolerant pipeline structure is used to process instructions. The hardware circuit structure of its control logic is shown in Figure 1. The pipeline structure consists of fetching components, decoding components, execution components, storage The access unit and the register writing unit are composed, and all the units of the above-mentioned pipeline structure are connected in sequence, and are connected with the first-line control and the backplane register; the output of the decoding unit and the storage access unit are also connected with an error correction processing unit, It is used to complete the error detection and correction of the source operand, and to establish corresponding control information. Each instruction is completed through five levels of processing under the control of the pipeline control and the backplane register; when the data in the register is correct, each The beat completes...

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Abstract

The invention discloses a method for achieving the five stage fault-tolerant stream line structure of microprocessor integral unit. The stream line structure is formed by an instruction folding part, a decoding part, a processing part, a storage visiting part and a back board register and is connected with a stream line controller and the back board register; there is an error correction processing part between the output of the decoding part and the storage visiting part which is used to finish the error detecting and correcting of the source operation number and establish the control information; each induction is controlled by the stream line and the back board register and is finished after five stage; when error correction processing part finds out the unit error, it corrects the error and sends it to the register writing part which can return the data to the back board register; then the stream line repetitive processes the current induction of PC and the next induction of nPC; if the error module finds out multiple bits error, it directly generates a trap, then stream line stops and enters into the trap processing program.

Description

technical field [0001] The invention belongs to the field of computer technology, and relates to the design and manufacture of a SPARC V8 compatible space computer microprocessor LSFT32, in particular to a method for realizing a five-stage fault-tolerant pipeline structure adopted in the integer unit (IU) of the LSFT32 microprocessor. Background technique [0002] Since IBM first proposed the idea of ​​a reduced instruction set in 1975, with the continuous development of microelectronics and computer technology, the reduced instruction set computer (reduced instruction setcomputer, RISC for short) has become the mainstream product in the current computer field. The main feature of RISC is that all operations performed by the microprocessor are register-oriented, and its main advantages are: [0003] (1) The operation instructions from register to register make full use of the high-speed on-chip bandwidth brought by the VLSI process for data transmiss...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 辛明瑞时晨张伟功靳加农
Owner CHINA AEROSPACE TIMES ELECTRONICS CORP NO 771 RES INST
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