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Realization of rapid coding-decoding circuit with run-length

A run-length, codec technology, applied in the field of fast run-length codec circuit implementation, can solve the problems of increasing pipeline delay and large circuit implementation scale, and achieves the effects of reducing power consumption, reducing implementation scale, and reducing pipeline delay.

Inactive Publication Date: 2006-05-31
CHIPNUTS TECH INC
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Problems solved by technology

[0010] The general-purpose run-length encoding and decoding hardware circuit has no problem in circuit function, but the circuit implementation scale is relatively large, and the scanning of each coefficient occupies a separate clock cycle. In terms of overall performance, the pipeline delay of one block processing is increased.

Method used

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  • Realization of rapid coding-decoding circuit with run-length
  • Realization of rapid coding-decoding circuit with run-length
  • Realization of rapid coding-decoding circuit with run-length

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Embodiment Construction

[0024] figure 1 It is a flow chart of setting the 64-bit non-zero flag bit register vector during 8×8 block processing (Block Processing). Before the quantization of the current block starts, the initial value of NZF[63:0] is 0. After the quantization starts, once the hardware circuit detects that the current quantization coefficient QC[i] is not zero, it will set the corresponding non-zero flag register position to 1, and when the quantizer outputs the last quantization coefficient NZF[63] of the current block, at the same time, the current A non-zero marker for a block completes.

[0025] figure 2 It is a real-time RLC encoding flow chart of run-length encoding during 8×8 block processing (Block Processing). When the actual circuit works, the RLC encoding of a non-zero coefficient is completed in two clock cycles. The first cycle is the prefetch coding cycle, and the second cycle is the RLC code readout cycle, but it is also the prefetch code cycle of the next non-zero ...

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Abstract

A method for realizing quick run length coding / decoding circuit includes marking nonzero coefficient while quantizing when run length is coded and finalizing real time RLC coding when Hoffman coding is carried on in system, obtaining RLC coding while finalizing counter ¿C scanning when run length is decoded and finalizing recovery of quantization coefficient when counter ¿C quantizing is carried on.

Description

Technical field [0001] The present invention adopts a novel hardware architecture, utilizes less hardware resources, and realizes fast run length code / run length decode (Run length code / run length decode) hardware circuit design. This invention can be directly applied to the design of digital graphics image compression and decompression hardware accelerator (such as JPEG hardware compression and decompression, dynamic video image compression and decompression) chip design, which effectively reduces the implementation scale of the run-length codec (RLC / RLD) circuit, and at the same time The hardware processing speed of the run-length encoding and decoding is improved, and the performance of the system as a whole is improved. Background technique [0002] At present, the implementation method of the more common run-length coding (RLC) hardware circuit is: [0003] (1) First, store the quantized coefficients output by the quantizer (Quantizer) based on block processing into th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T9/00
Inventor 唐宏斌
Owner CHIPNUTS TECH INC
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