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Read and erase verify methods and circuits suitable for low voltage non-volatile memories

A non-volatile, memory technology, applied in the technical field, can solve problems such as low operating voltage

Inactive Publication Date: 2012-03-21
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

While the four state, 3.0V design (corresponding to Vdd = 2.6V) may provide a sufficient safety margin to place read points between these state populations, these tolerances may change as the system moves to a later stage. more states, lower operating voltage, or both

Method used

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  • Read and erase verify methods and circuits suitable for low voltage non-volatile memories
  • Read and erase verify methods and circuits suitable for low voltage non-volatile memories
  • Read and erase verify methods and circuits suitable for low voltage non-volatile memories

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Embodiment Construction

[0021] For specific explanation, the following will be mainly based on a negative V th The first state represented by the value and one or more (here, 3) are represented by a V th The 4 states represented by >0V, 1.8V (Vdd=1.5V) are designed to illustrate the present invention. More generally, there will be one or more states characterized by a negative threshold and one or more states characterized by a positive threshold. When a specific memory system needs to be mentioned, this exemplary embodiment is a flash memory composed of a number of cells having one or more floating gates and usually having one or more select gates; for example, one is composed of several A NAND-type memory composed of a string of floating gate transistors connected in series with a select gate at one of its ends. Various applicable storage structures are described in the references incorporated in the background section.

[0022] Figure 2 illustrates the effect of operating conditions on a storage sys...

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Abstract

In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

Description

Technical field [0001] The present invention generally relates to non-volatile memory and its operation, and more specifically to technology. Background technique [0002] The principles of the present invention are applicable to various types of non-volatile memories-existing and expected non-volatile memories using new technologies currently under development. However, the construction scheme of the present invention is described in terms of a fast electrically erasable programmable read-only memory (EEPROM) in which the storage element is a floating gate. [0003] There are multiple architectures for non-volatile memory. One design of the NOR array connects its memory cells between adjacent bit (column) lines and connects the control gate to the word (row) line. Each individual cell either includes a floating gate transistor with or without a select transistor formed in series with it, or includes two floating gate transistors separated by a single select transistor. Examples...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/56G11C5/14G11C7/06G11C16/26G11C16/34
CPCG11C16/20G11C11/5628G11C16/344G11C7/04G11C16/26G11C16/3445G11C16/0483G11C11/5642G11C11/5635G11C16/3459G11C16/16G11C2211/5621G11C16/10
Inventor 陈健坎德克尔·N·夸德尔
Owner SANDISK TECH LLC