SCR controlled by the power bias

Abstract

A composite dual SCR circuit that acts to protect the Vcc node as well as an I / O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I / O node. When Vcc is low, the SCR protecting an I / O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I / O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to circuit protection from ESD (Electro Static Discharge, and more particularly to use of SCRs (Silicon Controlled Rectifiers) to protect against ESD events and latch up.[0003]2. Background Information[0004]Conventional ESD protection devices and methods include SCRs coupled across I / O (input / output) nodes that are directly coupled to the external environment and, thus, susceptible to external influences. Such SCRs are also connected across nodes that connect to power supplies. The protecting SCR, when positioned across two nodes (one node typically being ground), will present an open circuit to node voltages (meaning the voltage difference between the two nodes) less than the trigger or breakdown voltage of the SCR. When triggered by a voltage above the trigger voltage the SCR presents a low impedance across the pins as long as the node voltage is above the holding voltage of the SCR. Past...

AI Technical Summary

Problems solved by technology

Damage to devices typically can be described as a catastrophic voltage breakdown of an oxide layer that destroys the device or as latch up where a device unexpectedly remains turned on.

As the NMOS devices get smaller, latch up becomes more of an issue.

These transistors are biased off, but when stressed by over voltage, heat, radiation, etc. the PN junctions may become forward biased in a regenerative manner and draw excessive current.

Generally nodes that that connect to power supplies, e.g., Vcc, are more susceptible to latch up while I / O pins are more susceptible to ESD voltage breakdowns.

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