Phase error detection circuit, detection method and data recovery circuit

Abstract

The invention discloses a phase error detecting circuit and method and relative data restoring circuit, which is characterized by the following: the phase error detecting circuit detects the phase state of first group of gathered pulse signal and second group of gathered pulse signal, which contains advanced-and-delayed judgment circuit to receive the first and second gathered data sequence; the similarity of first and second gathered data sequence can be judged through detecting whether each phase of multiple data phase in the second gathered data sequence equals to one two-adjacent phase in the first gathered data sequence, which outputs the advanced signal and delayed signal selectively; the advanced-and-delayed accumulating circuit couples the advanced-and-delayed judgment circuit to receive the advanced signal and delayed signal, which generates the advanced-and-delayed accumulating signal according to the accumulated result.

Description

technical field [0001] The invention relates to a phase error detection circuit, a method and a related data recovery circuit, in particular to a circuit and a method for eliminating the phase error of a sampling pulse signal in a data recovery circuit. Background technique [0002] figure 1 It is a data transmission framework of a DVI (Digital Visual Interface) display system, which can be mainly divided into a computer host terminal 10 and a display terminal 20 . In the computer host terminal 10, the graphics card 12 is used to generate individual 8-bit image signals R[0:7], G[0:7] and B[0:7] of the three primary colors of red, green and blue; according to the DVI standard, The 8-bit image signal is transmitted to the DVI encoder 14 for encoding, and converted into 10-bit DVI image signals R'[0:9], G'[0:9] and B'[0:9]. Next, the DVI transmitter 16 converts the 10-bit DVI image signal into serial differential image signals [R+:R-], [G+:G-] and [B+:B-], and transmits them ...

AI Technical Summary

Problems solved by technology

However, since DVI data transmission occurs at extremely high rates, such as frequencies in the order of billions of hertz (GHz), it is quite difficult to generate such high-frequency sampling pulse signals

Furthermore, in data transmission with a frequency up to billions of hertz, the transmitted data signal is extremely susceptible to jitter and high-frequency reflection interference, which greatly reduces the effective sampling interval of data bits; this situation is shown in image 3 , affected by the reflection interference 38a, the effective sampling interval of the data bit 38 whose period is T is reduced to only T / 2, and beyond this T / 2 area may cause data interpretation errors

[0005] If when the sampling pulse signal deviates, the sampling pulse signal 32 is out of phase with the input data 30, so that the position of its sampling edge is not aligned with the central part 36 of the input data 30 data bits, then it is likely to get wrong sampling

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