Dual-voltage three-state buffer circuit

Abstract

A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

Description

technical field [0001] The present invention relates to an integrated circuit, and in particular to an improved design of a dual-voltage tri-state buffer circuit using a tri-state level shifter. Background technique [0002] The existing dual-voltage tri-state buffer includes a two-level shifter for controlling a post driver circuit, and it is composed of PMOS and NMOS transistors. The two-level shifter converts lower voltage signals into higher voltage signals. The post-driver circuit determines the output of the entire circuit by deciding which transistors are on or off. However, since PMOS transistors are driven more slowly than NMOS transistors, the time required to turn on or off PMOS and NMOS transistors is different. Since different input signals may establish different paths for signal transmission, and some paths may take more time, therefore, the time required for each level shifter to output signals is also different. According to these timing differences, in t...

AI Technical Summary

Problems solved by technology

[0007] Although buffer 100 reduces post-driver crossover current and uses two-level shifters 102 and 104 to convert low-level voltages to high-level voltages, due to timing issues, the inverters driving post-driver transistors 112 and 114 Ratio is too unstable

In addition, level shifters 102 and 104 and inverters 156 and 158 increase power consumption and circuit layout area

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