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Electrostatic discharge-protected integrated circuit

An integrated circuit, anti-static technology, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problem of large chip occupation space

Inactive Publication Date: 2006-11-01
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of achieving large capacitances is that a large footprint on the chip area is required for this, which is at odds with the ever-increasing miniaturization of components

Method used

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  • Electrostatic discharge-protected integrated circuit
  • Electrostatic discharge-protected integrated circuit
  • Electrostatic discharge-protected integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] figure 1 Shown is a semiconductor memory HS comprising an integrated circuit element ES for protection against electrostatic discharge and a memory cell zone SZ. The integrated circuit element ES for anti-static discharge protection is connected to the input terminal K1 for applying the supply potential V DD The terminal 1 is connected and is used to apply the supply potential V through the input terminal K2 SS terminal 2 connection. The circuit element is connected at the input to the memory cell zone SZ via terminals K6 and K7. The integrated circuit component ES for protection against electrostatic discharge connects the input terminal K1 to the output terminal K6 and the input terminal K2 to the output terminal K7. The transistor T is connected with its one drain and source connection T1 to the connection K1 and with its other drain and source connection T2 to the connection K2 . The control input T3 of the transistor is connected to node K3. The first capacito...

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PUM

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Abstract

An electrostatic discharge-protected integrated circuit comprises a transistor (T) which is connected by way of one of the drain and source terminals (T1, T2) to a connection (1) for applying a first supply voltage (VDD) and by way of one of the respective other drain and source terminals (T1, T2) to a connection for applying a second supply voltage (VSS). A first capacitor (C1) and a second capacitor (C2) are inserted as capacitive voltage dividers between the connection for applying the first supply voltage and the connection for applying the second supply voltage. The common dual node (K3) of the first and second capacitor is connected to the gate terminal (T3) of the transistor. If there is a discharge, the transistor is conducting and short-circuits a voltage that is not suitable for duly operating the functional unit between the connection (1) for applying the first supply voltage and the connection (2) for applying the second supply voltage.

Description

technical field [0001] The invention relates to an integrated circuit with antistatic protection. Background technique [0002] The electrostatic charge acceptable to humans is on the order of 0.6 μC. A human can be simulated by a capacitor with a capacitance of 150pF. If a charge of 0.6 μC is stored on a capacitor with a capacity of 150 pF, it corresponds to a charging voltage of about 4 kV. If a person carrying this voltage touches a grounded object, an electrostatic discharge can occur. This input discharges several amperes of current in about 0.1 μs. [0003] Electrostatic discharge processes distributed through MOS (=Metal Oxid Semiconductor) components often lead to component damage due to the small oxide layer thickness and dimensions of the conductor tracks and pn junctions. The discharge process mainly leads to a breakdown of the gate oxide or also to overheating of the pn junction or the conductor track. The energy converted during an electrostatic discharge i...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0266
Inventor M·B·索默
Owner INFINEON TECH AG