Circuit arrangement for supplying configuration data in FGPA devices

Abstract

A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

Description

technical field [0001] The following invention relates to a circuit arrangement for providing configuration data in an FPGA device. In particular, the circuit arrangement according to the invention allows the operation of output flip-flops provided in the configurable logic cells of the FPGA device in order to transfer such configuration data in the FPGA device using the configuration memory of the array of non-volatile memory cells . Background technique [0002] FPGAs (field programmable gate arrays) are integrated electronic circuits that can be fully programmed by the user ("in the field") and perform multiple logic functions desired by the user according to their programming or their configuration, respectively. Generally speaking, for this purpose, configurable logic blocks and configurable wiring resources are provided in the FPGA, and the electrical interconnection between them is determined by a plurality of switches that can be set by configuration bits. The logi...

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Problems solved by technology

For writing configuration data CD to non-volatile memory MCA via shift register ISR figure 2 The solution shown is also disadvantageous in the additional wiring expenditure caused by the coupling of the individual shift register cells Z1, Z2, ZN loading the shift register ISR to the bit lines BL1, BL2, BLN and by the shift register ISR itself. The increased circuit overhead of

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