Memory system and method of accessing memory chips of a memory system

Abstract

A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

Description

technical field [0001] The present invention relates to a memory system comprising a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connection lines are arranged in a specific topology, and to a method for this A method for accessing semiconductor memory chips of a memory system. Background technique [0002] Recent developments in fast semiconductor memories will lead to high-speed signal transfer rates of eg up to 7 Gbit / s. These high signaling rates require careful design considerations in terms of the implementation of a suitable topology and the proper method of accessing from the memory controller to the memory chips on the memory module. [0003] attached figure 1 Depicts a functional block diagram of an example of a heretofore known shared ring structure, which is a possibility of how to arrange a certain number of memory chips (eg, DRAM chips) on the memory module 100 in consideration of the connection ...

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Problems solved by technology

[0009] b) memory chips cannot be accessed in advance for certain setup procedures or for certain power-related procedures;

[0010] c) The memory chip cannot be accessed independently of the command and data flow;

[0011] d) According to figure 1 memory chips in a shared ring topology and according to figure 2 The main memory chip 210 in the star topology of must utilize the row and column selection included in the protocol to distinguish between redrive and memory chip read / write procedures, which results in higher logic effort;

[0012] e) Since the row and column selection command and clock enable information must be decoded when they are included in the protocol, even if only one redrive has to be performed in the memory chip, it involves body, therefore power dissipation increases

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