Chip package structure

Abstract

A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Description

technical field [0001] The present invention relates to a semiconductor package structure, in particular to a substrate on chip (substrate on chip, SOC) chip package structure. Background technique [0002] The so-called "Substrate on Chip" (Substrate on Chip, SOC) is a common semiconductor packaging structure. In this structure, a semiconductor chip is attached to a substrate with a plurality of holes, and a plurality of metal bonding wires are connected to the substrate and the chip through the holes. Usually, a plurality of solder balls arranged in a grid array are also formed on the substrate. In US Patent No. 6,190,943, a wafer-level packaging structure and packaging method are disclosed. As shown in FIG. 1 , it is a schematic cross-sectional view of a conventional wafer-level packaging structure. The WLP structure 20 includes a wiring substrate 22 , a semiconductor chip 24 , and a plurality of spherical solder balls 44 . Substrate 22 has an upper surface 30 for att...

AI Technical Summary

Problems solved by technology

Because it is semi-liquid during the heat and pressure process prior to attaching, the thermoplastic adhesive layer 28 in step (d) tends to overflow and thus cover the bond pads 36 of the die 24, thereby rendering the package ineffective.

[0006] 2. After applying the thermoplastic adhesive layer 28 in step (b), the substrate 22 cannot be stacked for shipping or storage

[0008] It can be seen that the above-mentioned existing chip packaging structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.

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