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H.264 integer transformation accelerator

A technology of integer transformation and row data, which is applied in the field of H.264 integer transformation acceleration devices, and can solve the problems of hardware scalability and fast transformation at the same time.

Inactive Publication Date: 2007-03-14
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the deficiency that the H.264 integer conversion device in the prior art cannot simultaneously have hardware scalability and fast conversion, the present invention provides a H.264 integer conversion that can be shared with other software on the hardware and has fast integer conversion acceleration device

Method used

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  • H.264 integer transformation accelerator
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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0125] See accompanying drawing: a kind of device of H.264 integer transformation acceleration, comprises the data memory connected with data bus, also comprises:

[0126] The vector operation working register group is used to receive the original data of the data memory, the original data is vector data: 4×4 input matrix; and the intermediate data of the accumulation register group;

[0127] Each vector operation register R i By 4 scalar operation registers R i0 , R i1 , R i2 , R i3 Composition, vector arithmetic working register R i It is used to store the i-th row of data of the 4×4 matrix or the i-th row of new data output by the accumulation register group.

[0128] 8-way vector data path, used to perform operations on 4×4 matrix row data according to operands;

[0129] The described 8-way vector data path process includes six levels of operations:

[0130] The first stage is 8 two-choice selectors, which are used to select the input from the accumulation register ...

Embodiment 2

[0155] H.264 transformation acceleration is preferably the following scheme, using H.264 integer cosine transformation acceleration:

[0156] When the controller is in the horizontal conversion mode, the data path reads the 4×4 matrix data in the data memory, and performs the following operations on the i row of data:

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Embodiment 3

[0204] H.264 transformation acceleration is preferably the following scheme, using H.264 integer arccosine transformation acceleration:

[0205] When the controller is in the horizontal conversion mode, the data path reads the 4×4 matrix data in the data memory, and performs the following operations on the i row of data:

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Abstract

This invention relates to H.264 integral number acieration device, which comprises the following parts: data memory connected to data bus; vector computation register set to receive original data as vector data; summing register set data with each register Ri composed of four work register RiO, Ri1, Ri2 and Ri3; eight path vector data connection to run data operation; sum register set to store Ri acieration middle data; controller to operate data and designing selection signals.

Description

(1) Technical field [0001] The invention relates to a device for H.264 integer transformation acceleration. (2) Background technology [0002] Previous video codec standards, such as MPEG2, MPEG4, etc. generally use 8×8 point discrete cosine transform (DCT) for transform coding. The latest video codec standard H.264 adopts 4×4 point integer transform, including integer cosine transform, integer inverse cosine transform and integer Hardman transform. Although, in terms of the computational complexity of a single block, compared with the 8×8 discrete cosine transform (DCT), the 4×4 point integer transform of H.264 reduces the amount of calculation a lot, but in the H.264 standard, the participation The number of integer transform blocks is very large, so under the same frame size of the video image, the cumulative integer transform calculation amount is much higher than that of 8×8 discrete cosine transform (DCT). Therefore, to realize the real-time codec of the video codec ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/24G06F15/80
Inventor 严晓浪秦兴刘大可葛海通罗晓华
Owner ZHEJIANG UNIV