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Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

A technology of etching and epitaxial layers, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc.

Active Publication Date: 2007-03-21
CREE INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While stacking faults affect a large portion of the active area of ​​the device, they tend to cause an increase in forward voltage in an undesirable mode, which can prevent the device from being as accurate and / or as needed or desired in many applications. operate effectively

Method used

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  • Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
  • Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites
  • Sequential lithographic methods to reduce stacking fault nucleation sites and structures having reduced stacking fault nucleation sites

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Embodiment Construction

[0062] The present invention will now be fully described hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions are exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements therein. As used herein, the ...

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Abstract

An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Description

[0001] Cross References to Related Applications [0002] This application claims Serial No. 60 / 554,123 filed March 18, 2004, entitled "Lithographic Method to Reduce Stacking Fault Nucleation Sites and Reduce V f Drift in Bipolar Devices and Structures Having ReducedStacking Fault Nucleation Sites", the disclosure of which is hereby incorporated by reference in its entirety as if fully set forth herein. [0003] Statement of Government Interest [0004] This application was developed under Government Contract No. N00014-02-C-0302. The U.S. Government owns a paid-up license in this invention and in limited circumstances requires the patentee to, under the terms of contract No. N00014-02-C-0302 awarded by the Defense Advanced Technology Research Projects Agency ("DARPA") The right to license others to use on reasonable terms. technical field [0005] The present invention relates to semiconductor materials and devices and methods of making them, in particular to methods of gro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/04H01L21/20H01L21/205
Inventor C·哈林H·伦登曼J·J·舒马克里斯
Owner CREE INC