System including a host connected serially in a chain to one or more memory modules that include a cache

Abstract

A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 60 / 470,078 filed May 13, 2003.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to computer system memory and, more particularly, to memory module configurations and the memory subsystem topology. [0004] 2. Description of the Related Art [0005] Many computer systems employ a main system memory that may be configured dependent upon the needs of an end user. In such systems, a motherboard or system board may include a number of memory expansion sockets. One or more small circuit boards, referred to as memory modules, may be inserted into the sockets as needed to increase the memory capacity of the computer system. Each of the memory modules typically includes multiple memory devices that provide a given amount of memory capacity. The memory devices are usually implemented using some type of dynamic random access memory (DRAM). Some examples of DRAM types include sync...

AI Technical Summary

Problems solved by technology

There are several drawbacks to parallel bus arrangements.

For example, depending on the topology of the interconnect, the maximum memory bus speed may be limited due to transmission line effects such as signal reflections.

Furthermore, increasing the size of the external cache may require a system redesign and so the external cache may not be configurable by an end user.

Although the operating speed of computer system processors continues to increase, the relative performance of the main system memory has not increased at the same rate.

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