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DRAM cell having MOS capacitor

a mos capacitor and mos technology, applied in the field of mos capacitors, can solve problems such as reducing refresh time, and achieve the effect of increasing the capacity of the mos capacitor and preventing current leakag

Inactive Publication Date: 2006-03-16
CHUNG CHENG HLDG LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The patent text describes a DRAM cell with a MOS capacitor that has increased capacity and prevents current leakage. The cell uses a plate node electrode as the active region of a substrate and a T-shaped storage node electrode on a trench in the substrate. The method for manufacturing the cell includes forming a trench on an active region of a substrate, implanting impurities, and depositing a conductive film to pattern the trench. The resulting material is then used to form a cell transistor and a MOS capacitor with a storage node electrode and a plate node electrode. A contact electrode and a wire are then formed to connect the cell transistor and the MOS capacitor. The technical effects of this patent include increased capacity and prevention of current leakage in the MOS capacitor."

Problems solved by technology

However, it is problematic in that data is stored in the well 12 which used as the storage node and thus a lot of leakage current results thereby reducing the refresh time.

Method used

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  • DRAM cell having MOS capacitor
  • DRAM cell having MOS capacitor
  • DRAM cell having MOS capacitor

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Embodiment Construction

[0023]FIG. 2 is a layout view of a disclosed DRAM cell having a MOS capacitor. Referring to FIG. 2, the disclosed DRAM cell layout includes a word line (gate electrode) 112 driven by a row address, a bit line 130 driven by a column address and a cell transistor having a source 118 connected to the bit line 113 and a gate electrode 112 connected to the word line. Also, a storage node electrode 114 is connected to a drain 118 of the cell transistor. Moreover, in the disclosed DRAM cell, a well 102, which is the active region of a semiconductor substrate, is used as a plate node electrode to constitute the MOS capacitor. A power line 134 is connected to the plate node electrode, which is the well 102 for supplying a power voltage via a contact electrode 132.

[0024] In FIG. 2, reference numerals 122, 124 and 126 denote contact electrodes. Reference numeral 11 denotes a mask region used when removing a film filled in the lower part of a trench upon the formation of a trench of the MOS ca...

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PUM

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Abstract

A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a plate node electrode which is a part of the active region, a storage node electrode having a T-shaped structure through a trench of the active region and an insulator thin film formed between the plate node electrode and the storage node electrode; a cell transistor having a gate insulating film and a gate electrode which are formed on the top surface of the active region and a source / drain formed within the active region; an interlayer insulating film deposited on a structure with the MOS capacitor and the cell transistor; a contact electrode connected with the source / drain of the cell transistor or with the storage node electrode of the MOS capacitor through a contact hole of the interlayer insulating film; a wire connected with the drain and the storage node electrode through the contact electrode; and a bit line connected with the source through the contact electrode.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This is a divisional of U.S. Ser. No. 10 / 737,052 filed Dec. 16, 2003, the entire disclosure of which is incorporated herein by reference.BACKGROUND [0002] 1. Technical Field [0003] A DRAM cell and a method for manufacturing the same are disclosed. More particularly, a DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed, which are suitable for electronic apparatuses such as a CD-R / W or game apparatus requiring a smaller memory capacity. [0004] 2. Description of the Related Art [0005] Generally, a semiconductor memory device denotes a device capable of storing data and reading it when necessary. It includes various kinds of semiconductor memory devices such as a DRAM (Dynamic Random Access Memory)-based semiconductor memory, a magnetic disc, an optical disc, and so on. Semiconductor memories have many advantages including compactness, high reliability, the ability to be produced at low cost and high speed...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/94H01L21/336H10B12/00
CPCH01L27/10861H01L27/10894H01L27/1087H01L27/10867H10B12/0385H10B12/0387H10B12/038H10B12/09
Inventor KIM, HAK-YUN
Owner CHUNG CHENG HLDG LLC