Structure and method of high performance two layer ball grid array substrate

Abstract

A high-performance, high I / O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.

Description

FIELD OF THE INVENTION [0001] The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure, materials and fabrication of high performance plastic ball-grid array packages designed for flip-chip assembly. DESCRIPTION OF THE RELATED ART [0002] Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input / output (I / O) count. BGA packages use sturdy solder balls for surface mount connection to the “outside world” (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years ev...

AI Technical Summary

Benefits of technology

[0011] According to the present invention, a high-performance, high input / output ball grid array substrate is provided, which is designed for integrated circuit flip-chip assembly and has two patterned metal layers and an intermediate insulating layer.

[0012] The insulating layer has a plurality of vias filled with metal, and one of the metal layers attached to each surface. Positioned between the two metal layers, the insulating layer has a thickness and material characteristics suitable for strong electromagnetic coupling between the signal lines and the first metal layer. In this manner, a predetermined impedance to ground is provided, and cross-talk between signal lines is minimized.

Problems solved by technology

The heat spreader is generally construed of copper and may include gold plating—representing an expensive part of the package.

As clock frequencies and current levels increase in semiconductor devices, the packaging designs are challenged to provide acceptable signal transmission and stable power and ground supplies.

The need, however, of high numbers of layers is contrary to the strong market emphasis on total semiconductor device package cost reduction.

The complexity and cost of the BGA packages are also influenced by the number of interconnections or vias that must be fabricated in the substrate layers to provide a path to connect each of the solder balls to either the ground plane, the power planes, or desired signal lines of the signal plane.

Generally, the metallization of the internal walls of each via increases the overall complexity.

Consequently, multiple vias and multiple substrate layers result not only in higher BGA fabrication costs, but also lower yields.

This approach, in turn, seems to greatly endanger the electrical and thermal package performance.

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