Nonvolatile ferroelectric memory device

Abstract

A nonvolatile ferroelectric memory device is provided so as to control read / write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read / write operations of the memory cell array.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a technology of controlling read / write operations of a nonvolatile ferroelectric memory cell using a channel resistance of a memory cell which is differentiated by polarity states of a ferroelectric material in a nano scale memory device. [0003] 2. Description of the Related Art [0004] Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and conserves data even after the power is turned off. [0005] The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelec...

AI Technical Summary

Benefits of technology

The present invention provides a nonvolatile ferroelectric memory device with improved data maintaining characteristics and reduced cell size. The device includes a floating channel layer with a P-type channel region and N-type drain and source regions, a bottom word line, insulating layers, and a word line. The device also includes a plurality of memory cells with a floating channel layer and a word line, and a plurality of sensing lines and bit lines arranged in a cross-cross pattern. The invention provides a method for controlling the read / write operations of the memory cell array to improve reliability and reduce the size of the cell.

Problems solved by technology

However, in the conventional nonvolatile FeRAM device, when the cell size becomes smaller, a data maintaining characteristic is degraded, so that it is difficult to perform the normal operation of the cell.

That is, a voltage is applied to an adjacent cell at read / write modes to destroy data of unselected cells, so that interface noise is generated between the cells and it is difficult to perform a random access operation.

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