Ferroelectric memory devices

Abstract

Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer. A conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes. Related structures are also discussed.

Description

RELATED APPLICATION [0001] This application claims the benefit of priority as a divisional application from U.S. patent application Ser. No. 10 / 273,115 filed Oct. 17, 2002, which claims priority from Korean Patent Application No. 2001-64252, filed on Oct. 18, 2001. The disclosures of the above referenced U.S. and Korean patent applications are incorporated herein in their entirety by reference.FIELD OF THE INVENTION [0002] The present invention relates to ferroelectric random access memory (FRAM) devices and related methods of fabrication. BACKGROUND OF THE INVENTION [0003] A ferroelectric material exhibits polarization when an external electric field is applied, and maintains the polarization even after removing the external electric field. Also, ferroelectric materials may control a direction of spontaneous polarization with a change of the electric field. Ferroelectric materials include PZT[Pb(Zr, Ti)O3], SBT[SrBi2Ta2O9], and the like. These characteristics of ferroelectric mater...

AI Technical Summary

Benefits of technology

This approach allows for the economic fabrication of ferroelectric memory devices with sufficient capacitance and reduced misalignment, enhancing the reliability of semiconductor devices by minimizing additional fabrication steps and maintaining high capacitance.

Problems solved by technology

However, as an integration level of a semiconductor memory device increases, a cell area of individual FRAM devices may decrease.

In addition, some FRAM electrode materials may not be desirable as storage node contacts due to a relatively high electrical resistance and / or relatively poor gap fill characteristics.

In this case, however, a node separation process of the lower electrode may be difficult to provide using chemical mechanical polishing (CMP).

Accordingly, the cylinder-type COB capacitor structure may not be suitable for FRAM devices.

In addition, a stacked capacitor structure may not be suitable for FRAM devices.

Because most of a high-priced material making up the lower electrode layer may be removed, fabrication costs may be unnecessarily increased.

Also, an etch process for forming the lower electrode may be difficult to perform.

Therefore, a likelihood of misalignment may be increased while patterning the upper interlayer insulating layer, and misalignment may cause a decrease in a contact area between the upper and lower contact plugs.

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