Packaging structure and method
a packaging structure and chip technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of poor electrical contact, reduce the reliability of the package, and reduce the reliability of the bonding interfa
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[0013] A description of an exemplary embodiment of the invention follows. Using the disclosure herein, substantially conventional apparatus can be modified for use in the process of the invention.
[0014] With reference to the Figs., there are shown in FIG. 1A a chip and a substrate in alignment prior to forming the interconnect according to the invention, and in FIG. 1B a completed interconnect. The flip chip configuration, shown generally at 10, includes a plurality of bumps, e.g. 14, formed on the chip 12, the bumps preferably being gold (Au) stud bumps. The corresponding interconnection points, on a standard substrate 16 metallization are provided with a plurality of preferably pure tin (Sn) spots 18. A central area 20 of the chip on a bump side 22 further includes a spot of adhesive 24 small enough that it does not spread to the gold studs and the interconnection area during a subsequent bonding process. As the chip is connected to the substrate in the flip chip format, the adhe...
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