Non-volatile semiconductor memory

Abstract

A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of “0”s are stored into the second memory area, and an equal number of “0”s and “1”s are stored in the memory cells of the first memory area. The memory cells of the first memory area are read using an initial first reading voltage. The first reading voltage is adjusted and the memory cells of the first memory area are re-read until an equal number of “0”s and “1”s are read out of the memory cells of the first memory area, to thereby obtain a final first reading voltage. An initial second reading voltage is determined on the basis of the final first reading voltage. The memory cells of the second memory area are read using the initial second reading voltage. The second reading voltage is adjusted and the memory cells of the second memory area are re-read until the number of “0”s read is equal to the number of “0”s stored in the second memory area, thereby obtaining a final second reading voltage. The final second reading voltage is used as a reading voltage for reading the memory cells of the semiconductor memory.

Description

FIELD OF THE INVENTION [0001] The present invention relates to non-volatile semiconductor memories and to methods for determining reading voltages for reading data out of the memory cells of such memories. BACKGROUND OF THE INVENTION [0002] The storage capacity of flash memories can be increased by increasing the number of bits stored per memory cell. Nitride programmable read-only memory (NROM) cells are non-volatile memory cells that can store two bits per cell. FIG. 1 shows a sectional view through an NROM cell as known in the prior art. In a memory, the gate G of the cell will be connected to a wordline and the two source / drain regions S / D will be connected to bitlines. Below the gate G is the so-called ONO layer which consists of a nitride layer NL sandwiched between a top oxide layer TO and a bottom oxide layer BO. Electric charge can be stored in the nitride layer NL at a first location B1 and at a second location B2. The amount of charge stored in each location can be adjust...

AI Technical Summary

Benefits of technology

[0015] The invention further provides a non-volatile semiconductor memory comprising a plurality of memory cells organized in a first memory area and in a second memory area, a wordline decoder connected to the first memory area and the second memory area, a plurality of sense amplifiers connected to the first memory area and the second memory area, a reading voltage control unit connected to the plurality of sen

Problems solved by technology

Once the distributions of the erased and programmed memory cells overlap, it is no longer possible to distinguish between programmed and erased cells.

If ten to twenty steps are needed for reading data with strongly shifted threshold voltage distributions, the response time is long and the reading performance of such a memory is poor.

Additionally, repeatedly reading all the memory cells leads to an increase in power consumption, which is especially undesirable if the semiconductor memory is used in mobile devices.

However, this leads to the problems illustrated in FIGS. 3B, 3C, 3D.

This leads to wrong data and reading failures.

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