Parameterizable clip instruction and method of performing a clip operation using the same

Abstract

A parameterizable clip instruction for SIMD microprocessor architecture and method of performing a clip operating the same. A single instruction is provided with three input operands: a destination address, a source address and a controlling parameter. The controlling parameter includes a range type and a range specifier. The range type is a multi-bit integer in the operand that is used to index a table of range types. The range specifier plugs into the range type to define a range. The data input at the source address is clipped according to the controlling parameters. The instruction is particularly suited to video encoding/decoding applications where interpolations or other calculations, lies outside the maximum value and that final result will have to be clipped to saturation value, for example, the maximum pixel value. Signed and unsigned clipping ranges may be used that are not only powers of two.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Provisional Patent Application No. 60 / 721,108 titled “SIMD Architecture and Associated Systems and Methods,” filed Sep. 28, 2005, the disclosure of which is hereby incorporated by reference in its entirety.FIELD OF THE INVENTION [0002] The invention relates generally to embedded microprocessor architectures and more specifically to a clip instruction for SIMD microprocessor architectures and a method of performing a clip operation using such a clip instruction. BACKGROUND OF THE INVENTION [0003] Single instruction multiple data (SIMD) architectures have become increasingly important as demand for video processing in electronic devices has increased. The SIMD architecture exploits the data parallelism that is abundant in data manipulations often found in media related applications, such as discrete cosine transforms (DCT) and filters. Data parallelism exists when a large mass of data of uniform ty...

AI Technical Summary

Benefits of technology

[0007] Thus, there exists a need for a SIMD microprocessor architecture that ameliorates at least some of the above-noted deficiencies of conventional systems. At least one embodiment of the invention may provide a parameterizable microprocessor clip instruction. The parameterizable microprocessor clip instruction according to this embodiment may comprise a destination register operand, a source register operand of a value to be clipped, and a second source operand containing the control parameter specifying the manner in which clipping is to be performed, wherein the control parameter comprises a range type and range specifier. It should be appreciated that in the context of a SIMD machine, the source operand containing the “value” to be clipped is really referring to the values to be clipped because a 128-bit register is used to hold 8 16-bit values to be clipped by a single instruction.

Problems solved by technology

Such a software clipping implementation incurs a high overhead due to the number of calculations required to test each value.

The sequential nature of a software implementation makes it very difficult to be optimized in processors designed to exploit instruction level parallelism, such as, for example, SISD reduced instruction set (RISC) machines or very long instruction word (VLIW) machines.

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