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Data retention in a semiconductor memory

a technology of semiconductor memory and data retention, applied in the field of data processing systems, can solve problems such as difficulty in a signal from one voltage domain

Active Publication Date: 2007-07-12
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor memory storage device that solves the problem of power loss in SRAM by providing two voltage domains with different voltage levels. The data retention portion is powered by a different voltage level than the peripheral portion, and a power switching device is used to reduce the voltage difference across the latches during a write request. The device uses a write assist signal to selectively isolate the data storage portion from the data input and provide a low impedance path between the data port and the data storage portion. The device also allows for writing to multiple latches simultaneously and controls the data transfer enable signal to selectively isolate the storage device from the data input. The technical effects of this invention include reducing power loss, improving performance, and reducing leakage retention.

Problems solved by technology

A potential problem with two voltage domains is that it may be difficult for a signal from one voltage domain (the peripheral portion) to switch the state of a latch in a different voltage domain.

Method used

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Examples

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Embodiment Construction

[0042]FIG. 1 shows a simplified diagram of a SRAM 10. The SRAM 10 comprises a data retention portion 20, the data retention portion 20 comprising an array of 6T-cells. These are conventional data retention cells formed from six transistors (see FIG. 3). There is also a peripheral portion comprising precharge and write logic 32, sense amplifiers 34, decoders and word line drivers 36 and address latches and miscellaneous logic 38. SRAM circuits 10 are known and traditionally the entire circuit is in a single voltage domain. In embodiments of the invention, by contrast, the data retention portion 20 is formed in a different voltage domain to the peripheral portion.

[0043] In order to save power, the circuit may operate in a sleep mode, wherein during inactive periods, power can be reduced to portions of the circuit to reduce power consumption. To avoid a loss of state it is advantageous to retain power to the data retention portion 20, however the peripheral portions may be turned off....

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PUM

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Abstract

The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to the field of data processing systems. More particularly, this invention relates to the field of semiconductor memories. [0003] 2. Description of the Prior Art [0004] In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency attention is also being turned to reducing static power loss, i.e. power loss due to currents occurring while a circuit is not performing operations. One solution to this issue is to simply turn off the supply to a portion of the design that is not currently being used. This serves to save static power, but there are significant dynamic power costs associated with restoring the state of the system when power is once again supplied to that portion of the design. Furthermore, there are additional drawbacks ass...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C5/14
CPCG11C11/417G11C5/14
Inventor FREDERICK, MARLIN
Owner ARM LTD