BEOL compatible FET structure

Abstract

This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is related to application Ser. No. ______, also entitled “BEOL compatible FET Structure,” Attorney Docket No. YOR920050395US2, assigned to the same assignee as the present application, and filed on the same date herewith, the contents of which are incorporated herein by reference in their entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention generally relates to the fields of semiconductor integrated circuits and electrical interconnect technology, and more particularly relates to vertical or 3D integration of devices such as thin film transistors (TFTs) into back end of the line (BEOL) interconnect structures. [0004] 2. Description of the Related Art [0005] In recent years 3D integration has gained significant attention as a possible pathway for increasing IC density and for reducing interconnect delays and ac power consumption (by reducing interconnect distances). [0006] In one pri...

AI Technical Summary

Benefits of technology

The present invention provides an electrical interconnect structure that allows for the incorporation of thin film transistors without using high temperature processes that could damage the underlying silicon device level. The structure includes a plurality of layers with interconnecting line and / or via structures and thin film transistors with self-aligned overlap between the source and drain regions and the gate electrode. The thin film transistors can be formed from a polycrystalline semiconductor film that can be deposited at low temperatures. The structure also allows for the incorporation of p-type and n-type thin film transistors in a single interconnect level. The method of forming the structure is cost-effective and compatible with existing dual damascene processes. The invention provides a way to reduce circuit area and footprint of the integrated circuit.

Problems solved by technology

Although these devices can have an inferior mobility and lon / loff ratio compared to advanced single crystal silicon devices due to the grain boundaries in the polycrystalline film, these devices are targeted toward applications that do not require the high performance of the standard single crystal silicon devices in the bottom level.

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