Parallel Electronic Design Automation: Shared Simultaneous Editing

a technology of electronic design and shared editing, applied in the direction of instruments, symbolic schematics, cad techniques, etc., can solve the problems of user limitation, user cannot see the edits made to the rest of the board while, and there is no known mechanism that allows users to simultaneously work in shared areas of a pcb design. to achieve the effect of preserving the integrity of the design

Inactive Publication Date: 2008-03-06
MENTOR GRAPHICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008] In one aspect of the invention is a method for simultaneously allowing multiple users to edit in shared areas of a master design. The method includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Problems solved by technology

However, this approach is restrictive in that the user is limited to viewing only areas of the design that are opened by each individual.
Consequently, the user cannot see edits that are made to the rest of the board while the user's edits are being made.
Furthermore, there is currently no known mechanism that allows users to simultaneously work in shared areas of a PCB design while maintaining the integrity of the PCB design.

Method used

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  • Parallel Electronic Design Automation: Shared Simultaneous Editing
  • Parallel Electronic Design Automation: Shared Simultaneous Editing
  • Parallel Electronic Design Automation: Shared Simultaneous Editing

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Embodiment Construction

[0024] In one aspect of the invention is a method for allowing a user to edit a PCB design concurrently with allowing the user to view edits to the PCB design by other users. Generally, the method displays a PCB design to a plurality of users. While a first user makes edits to an arbitrary section of the PCB design, a second user makes edits to an arbitrary section of the PCB design while preserving the integrity of the master design. In one embodiment of the invention, arbitrary sections may overlap, allowing each user to edit shared areas of the master design. In another embodiment of the invention, arbitrary sections are mutually exclusive, such that each user edits unshared, exclusive areas of the master design.

[0025] The present invention includes various operations, which will be described below. The operations of the present invention may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or...

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Abstract

A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a division of U.S. patent application Ser. No. 10 / 780,902, filed Feb. 19, 2004 and titled “Parallel Electronic Design Automation: Shared Simultaneous Editing,” which application is a continuation of U.S. patent application Ser. No. 10 / 269,614, filed Oct. 10, 2002 and titled “Parallel Electronic Design Automation: Shared Simultaneous Editing” (now U.S. Pat. No. 6,708,313) which application claims the benefit of U.S. Provisional Application Ser. No. 60 / 341,037, filed Dec. 10, 2001. All of said applications are incorporated by reference herein.COPYRIGHT NOTICE [0002] A portion of the disclosure of this patent document may contain material which is subject to copyright protection. To the extent that it does, the copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise rese...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F17/50G06F17/30H05K3/00
CPCG06F17/50G06F2217/74G06F17/5068G06F2111/12G06F30/00G06F30/39G06F2115/12
Inventor PFEIL, CHARLESSMITH, EDWIN FRANKLINPETUNIN, VLADIMIRPOTTS, HENRYNATARAJAN, VENKAT
Owner MENTOR GRAPHICS CORP
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