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Shallow trench isolation structure for shielding trapped charge in a semiconductor device

a technology of isolation structure and semiconductor device, which is applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve problems such as device malfunction of electrical structures

Inactive Publication Date: 2008-05-22
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor structure and a method for forming it. The semiconductor structure includes a first field effect transistor (FET) with a channel region, a source structure, a drain structure, a gate dielectric, and a gate electrode. The structure also includes a shallow trench isolation (STI) structure that isolates the first FET from a second FET. The STI structure includes a dielectric liner, a conductive STI fill structure, and a dielectric cap layer. The conductive STI fill structure has a top surface that is above the first FET by a first distance and is above the second FET by a second distance that is less than the first distance. The invention provides a system and method for protecting devices from unwanted electrical charges.

Problems solved by technology

Unwanted electrical charges within an electrical structure may cause devices within the electrical structure to malfunction.

Method used

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  • Shallow trench isolation structure for shielding trapped charge in a semiconductor device
  • Shallow trench isolation structure for shielding trapped charge in a semiconductor device
  • Shallow trench isolation structure for shielding trapped charge in a semiconductor device

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Embodiment Construction

[0021]FIG. 1 illustrates a perspective view of a semiconductor structure 2 comprising a shallow trench isolation (STI) structure 11, in accordance with embodiments of the present invention. The semiconductor structure 2 comprises a silicon substrate 10, a field effect transistor (FET) 21, a FET 23 (only partially shown in FIG. 1), and the STI structure 11 (i.e., comprising a dielectric liner 36, a conductive STI fill structure 32, and a dielectric cap structure 34). The STI structure 11 is located within a trench (i.e., see trench 40 in FIG. 5B) formed in the silicon substrate 10 between the FET 21 and the FET 23. The STI structure 11 physically and electrically isolates the FET 21 from the FET 23. The following description of FET 21 also applies to FET 23. The FET 21 comprises a source structure 48a, a drain structure 48b, a gate dielectric layer 14, a shared gate electrode 16 (i.e., the gate electrode 16 is shared by the FET 21 and the FET 23), and a channel region 24. The channel...

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Abstract

A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

Description

[0001] This application is a continuation application claiming priority to Ser. No. 11 / 276,132, filed Feb. 25, 2006.BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to a structure and method to shield a trapped charge from devices within a semiconductor structure. [0004] 2. Related Art [0005] Unwanted electrical charges within an electrical structure may cause devices within the electrical structure to malfunction. Therefore there is a need for protecting devices within an electrical structure from the affects of unwanted electrical charges. SUMMARY OF THE INVENTION [0006] The present invention provides a semiconductor structure, comprising: [0007] a first field effect transistor (FET) comprising a channel region formed from a portion of a silicon substrate, a source structure formed adjacent to said channel region, a drain structure formed adjacent to said channel region, a gate dielectric formed over said channel region, and a gate electro...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/088
CPCH01L29/7833H01L21/76224
Inventor CANNON, ETHAN HARRISONCHANG, SHUNHUA THOMASFURUKAWA, TOSHIHARUHORAK, DAVID VACLAVKOBURGER, CHARLES WILLIAM III
Owner GLOBALFOUNDRIES INC