CMP related scratch and defect improvement
a technology of defect improvement and scratching, applied in the field of semiconductor processing, can solve problems such as defects that are formed after a particular polishing process is completed, defects that cannot be removed by the subsequent polishing or buffing process, and scratches deep or strongly adherent particles or residues
Inactive Publication Date: 2008-06-26
TEXAS INSTR INC
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Benefits of technology
[0007]Therefore, a need has arisen for processes that overcome these and other shortcomings of the related art. The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overvi
Problems solved by technology
It is at this time that some particles between the wafer and the polishing and buffing pads may cause defects on the wafer.
Further, defects that are formed after a particular polishing process is completed, such as deep scratches or strongly adherent particles or residues, may not be removable by the subsequent polishing or buffing process.
Method used
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[0017]The present invention is directed towards chemical-mechanical polishing (CMP) of a workpiece, wherein defects are generally mitigated. Accordingly, the present invention will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. It should be understood that the description of these aspects are merely illustrative and that they should not be taken in a limiting sense. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident to one skilled in the art, however, that the present invention may be practiced without these specific details.
[0018]Referring now to the figures, FIG. 1 illustrates an exemplary multiple-polishing CMP apparatus 100 for substantially removing one or more layers (not shown) disposed on a plurality of semiconductor wafers 110. The one or more layers, for exa...
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Abstract
A method for serially polishing a plurality of semiconductor wafers, wherein a CMP apparatus having a first polishing pad and a second polishing pad is provided. A first slurry composition is disposed between the first polishing pad and a first wafer when the first wafer is in a first state, and a first polishing on the first wafer via the first polishing pad and first slurry composition is commenced at a first commencement time. A second slurry composition is disposed between the second polishing pad and a second wafer when the second wafer is in a second state, and a second polishing on the second wafer via the second polishing pad and second slurry is commenced at a second commencement time, wherein the second commencement time differs from the first commencement time by a first intermediate period. One or more of the first wafer and the second wafer is rinsed with a pre-rinse agent for at least a portion of the first intermediate period. The first polishing and second polishing are halted at substantially the same end time, therein placing the first wafer in the second state and the second wafer in a third state.
Description
REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority to Ser. No. 60 / 876,740 filed Dec. 22, 2006, which is entitled “CMP Related Scratch and Defect Improvement”.FIELD OF THE INVENTION[0002]The present invention relates generally to semiconductor processing, and more particularly to a method for chemical-mechanical polishing (“CMP”) of a workpiece. Specifically, the present invention relates to processes for reducing defects on a semiconductor wafer.BACKGROUND OF THE INVENTION[0003]Some known chemical-mechanical processes for polishing a semiconductor wafer may include forming a dielectric layer over the semi-conductor substrate, etching a plurality of trenches into the dielectric layer, and forming a barrier layer over the dielectric layer and the trenches. These known processes also may include forming a copper seed layer over the barrier layer and forming a copper layer over the copper seed layer, such that a portion of the copper seed layer and a portion of the ...
Claims
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CPCB24B37/042
Inventor CHEN, LINLINCHEN, LIPAPA RAO, SATYAVOLU SRINIVAS
Owner TEXAS INSTR INC