System and method for realizing network synchronization by packet network
a network synchronization and packet network technology, applied in the field of communication, can solve the problems of failure to meet the requirement of circuit service, cannot guarantee the transmission delay or the transmission sequence of packets, and achieve the effect of high bandwidth of the ip packet network
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first embodiment
[0042]According to the present invention, the framework of a network device capable of IP synchronization is illustrated in FIG. 1. The network device may be one of a plurality of processing devices at different levels, and the processing device includes a transmission module and a reception module. The transmission module may be provided in a downlink interface board, and the reception module may be provided in an uplink interface board. A switching backplane and a master control board may be provided between the uplink interface board and the downlink interface board. Particularly, the switching backplane may be an Ethernet switching backplane or other IP packet network switching backplanes.
[0043]The uplink interface board exchanges data with a processing device at upper-level over a data link via an interface of the uplink interface board. When data is required to be received from the processing device at upper-level, the uplink interface board recovers a clock signal from the da...
second embodiment
[0063]A method according to the present invention is illustrated in FIG. 4.
[0064]Block 101: In a processing device, Data transmitted from a processing device at upper-level in a packet network is received over a data link and a clock signal is recovered from the data link.
[0065]Block 102: In the processing device, the recovered clock signal and the data signals are mixed and then the mixed signals are transmitted to a processing device at lower-level.
[0066]Block 103: The lower-level processing device recovers the clock signal from the data link.
[0067]Block 104: The clock signal is adaptable to be provided for a clock signal for the processing device at lower-level system itself. The processing device at lower-level mixes the clock signal and the data signals and transmits the mixed signals over a data link to a processing device at further lower-level.
[0068]The processing device at further lower-level proceeds with the block 103.
[0069]An implementation procedure according to the sec...
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