Barrier dielectric stack for seam protection

Abstract

The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Description

RELATED APPLICATIONS[0001]This application is a divisional application of U.S. Ser. No. 10 / 904,661, filed Nov. 22, 2004.FIELD OF THE INVENTION[0002]The present invention relates to semiconductor devices having enhanced resistance to shorting, and more particularly to metal oxide semiconductor field effect transistors (MOSFETS), in which electrical shorting between the gate conductor and the contacts to the source and drain regions of the device is substantially eliminated by a conformal dielectric passivation stack positioned on at least the sidewalls of the gate region. The inventive conformal dielectric passivation stack comprises at least a first conformal dielectric layer and a second conformal dielectric layer in which no electrical pathway is present that extends entirely through the stack. The absence of the electrical pathway can be achieved by using a second conformal dielectric that is seamless or one in which the seams are offset from the seams present in the first dielec...

AI Technical Summary

Benefits of technology

[0009]When the second dielectric layer of the dielectric stack includes seams, the seams of the second dielectric are offset from the seams present in the first dielectric layer therefore providing a discontinuity in the electrical pathway within the deposited layers caused by the seams being aligned. By depositing multiple dielectric layers atop one another, any seams present in the dielectric layers are covered or offset from one another, therefore providing a conformal dielectric layered stack having a discontinuous electrical pathway. In the present invention, the passivation stack thus has discontinuous seams. The term “discontinuous seams” denotes that the seams of each dielectric layer within the conformal dielectric layered stack are covered or offset from one another in a manner that would substantially eliminate electrical paths between the gate conductor and contact of FET devices of current and future generations of scaling.

[0010]Broadly, the inventive semiconducting device comprises:a gate dielectric atop a semiconducting substrate, said semiconducting substrate containing source and drain regions adjacent said gate dielectric;a gate conductor atop said gate dielectric;a conformal dielectric passivation stack positioned on at least said gate conductor sidewalls, said conformal dielectric passivation stack containing a discontinuous electrical pathway; anda contact to said source and drain regions, wherein said conformal dielectric passivation stack substantially eliminates shorting between said contact and said gate conductor.

Problems solved by technology

This electrical path can, in turn, result in device shorting.

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