Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions

Abstract

A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers.

Description

TECHNICAL FIELD[0001]The present invention relates to the field of integrated circuits, and more particularly that of transistors, and aims to present a microelectronic device provided in particular with a multi-branch channel structure, or a multi-channel structure, and a so-called “surrounding” gate having a uniform critical dimension as well as means to insulate this gate from the source and drain regions, the device being improved in terms of electrical performances, in particular with regard to the parasitic capacitances between the gate and the source and drain regions. The invention also includes a method for fabricating a device of this type.PRIOR ART[0002]A traditional transistor structure is generally formed, on a substrate, for example of the SOI (silicon on insulator) type, by a source region and a drain region, for example in the form of a first and a second semiconductor zone, respectively, these zones being connected to each other via a third semiconductor structure i...

AI Technical Summary

Benefits of technology

[0022]According to one possibility, the second material and / or the first material can be a given semiconductor comprising an additive, the additive being formed by atoms of a size different from that of said semiconductor, the additive being made up of smaller atoms than the atoms of said given semiconductor for example when said given semiconductor is stressed in biaxial compression in the plane of the support, or being made up of atoms larger than the atoms of said given semiconductor, for example when said given semiconductor is stressed in biaxial tension in the plane of the support. In the case where the given material is SiGe in biaxial compression, the additive can for example be in the form of carbon or boron atoms. The presence of this type of additive in the first material or in the second material may make it possible to offset the stress that one of said first material and second material applies on the other of said first material and second material, and make it possible to have a stack provided with a high number of thin layers, without the electrical properties of the device being altered.

[0048]According to one advantageous embodiment, the film of the stack which is in contact with the support, is a sacrificial layer based on the second material. This can make it possible to form semiconductor bars which are not in contact with the support and a totally surrounding gate, forming a ring around each of said semiconductor bars.

[0049]According to one variation for which the support comprises a dielectric film whereon said stack is formed, the method can also comprise: after step b) and before step d), a partial removal of the dielectric layer through the cavity. This can also make it possible to form semiconductor bars which are not in contact with the support and a totally surrounding gate, forming a ring around each of said semiconductor bars.

Problems solved by technology

The gate structure obtained using this type of method comprises overlap parasitic capacitances between the gate and the source and drain regions, which damage the electrical performance of the transistor.

The problem arises of finding a new microelectronic device comprising a channel structure transistor comprising several branches or with a multi-channel structure, provided with a “surrounding” or “semi-surrounding” gate, which does not comprise the abovementioned drawbacks, as well as a method making it possible to implement a device of this type.

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