Method for link bandwidth management

a bandwidth management and link technology, applied in the direction of transmission, electrical equipment, instruments, etc., can solve the problems of complicated and time-consuming, insufficient preset bandwidth, and insufficient link bandwidth, etc., to achieve fast link bandwidth change, high power efficiency, and good performance

Inactive Publication Date: 2008-11-27
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]The present invention provides a method for link bandwidth management targeted to achieve both good performance and high power efficiency for any specific application and to have a fast link bandwidth change for ameliorating the above-mentioned defects of conventional technology.
[0009]The present invention provides a method for link bandwidth management between two devices in communication through a bus in a computer system, which includes: monitoring whether a change condition of the bus having a link is activated; changing a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated; and causing the bus to operate at the target bandwidth without disabling the link or powering down the computer system.

Problems solved by technology

Since the execution of link down / initial power up state 50 and device initial / configuration state 56 to change link width / speed is complicated and time consuming.
Moreover, for bandwidth eager applications, e.g. 3D game software, the preset bandwidth may be too small; and for applications with few packets traffic, e.g. document software, the preset bandwidth is often too luxury for them, which in most cases means power waste.

Method used

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Examples

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Embodiment Construction

[0017]As depicted in FIG. 3, it is an embodiment of link bandwidth management a PCI express bus according to the present invention. In the embodiment, the PCI express bus changes link width / speed when a change condition is activated. The change condition according to the invention can be a hardware autonomous change, a software-directed change, or an unreliable change; and each change includes link width change and link speed change.

[0018]As depicted in FIG. 3, the software-directed change includes software-directed speed change 104 and software-directed width change 122. When a computer system is executing a software application, the software application stores a required link width / speed for the PCI express bus in a register of a north bridge chip. The link width / speed need to be changed if the link width / speed stored in the register is different from the present link width / speed. For example, if the initial link width / speed of the PCI express bus is link A / B 100, and the link wid...

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PUM

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Abstract

A method for link bandwidth management between two devices in communication through a bus in a computer system. Whether a change condition of the bus having a link is activated is monitored. Change a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated. The bus will operate at the target bandwidth without disabling the link or powering down the computer system if subsequent failure speed management and unreliable speed management have passed.

Description

CROSS REFERENCE TO RELATED PATENT APPLICATION[0001]This patent application is a continuation application (CA) of U.S. patent application Ser. No. 10 / 490,349, filed Jul. 20, 2006, and now pending. The contents of the related patent application are incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to a method for link bandwidth management, and more particularly to a method for link bandwidth management applied to a PCI express bus.BACKGROUND OF THE INVENTION[0003]As shown in FIG. 1, it is a computer system architecture. In a modern computer system, CPU 20, memory 22, and graphic chip 24 work very closely and they need to have faster data access to each other. As a result, requests and responses issued from the three devices are all controlled and managed by the north bridge chip 26. The north bridge chip 26 is tied to the south bridge chip 28, which routes traffic from the different I / O devices on the system, such as hard disk drive 30, optical...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F13/40G06F13/20
CPCH04L41/0896
Inventor MAO, JIN-LIANG
Owner VIA TECH INC
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