Smart-card chip arrangement
a chip arrangement and card chip technology, applied in the field of smart card chip arrangement, can solve the problems of chip refusing to continue operation, loss of encryption key, and depackaging procedure leaving the protection grid inta
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first embodiment
[0047]a smart-card chip arrangement in accordance with the invention is illustrated in FIGS. 1 and 2. In FIG. 1 a smart-card chip 10, which may be a standard chip supplied by a suitable supplier, has applied to its upper surface a single organic conductive layer 12. The organic conductive layer 12, which, as already stated, may have conducting or semiconducting properties, is applied as a strip of material in a grid configuration over the upper surface of the chip 10. This strip is connected at its two ends to respective bond pads 14, 16, which in turn are connected to suitable control circuitry located on the chip. The control circuitry provides operating signals for at least indirectly assessing the properties of the organic layer.
[0048]In this embodiment the layer is used as an RC (resistor-capacitor) delay line and the control circuitry feeds a pulse into one end of the delay line and measures the time it takes for the pulse to reach the other end. An alarm is triggered if the r...
third embodiment
[0056]FIG. 6 shows the corresponding sequence of events for the third embodiment shown in FIG. 4. Before a card containing the smartcard chip is issued, the protection layer is “read” by determining its response to an input pulse. This is the pre-characterizing phase. As already explained, this response is in the form of a delay time, which is used in conjunction with a set of pre-key bits in non-volatile memory 28 to derive the cryptographic key for the chip at the output of the transform logic circuit 40. Subsequently, when the smartcard is used, it is inserted into a card reader, which powers on the card (step S120). The protection layer is then re-read in a characterisation step (S122), which derives the key once again (step S124) based on the updated properties of the protection layer. If those properties remain the same, the key will remain the same, indicating that the layer has not been damaged and so tampering has not occurred. Consequently, the transaction (e.g. the withdr...
fourth embodiment
[0062]The use of at least two separate protection layers allows the use of the invention, which is illustrated in FIG. 10. In this embodiment a first organic protection layer, which is modelled as an RC network 70 in FIG. 10, is formed as a lower layer (e.g. the layer 62 in FIG. 9), while a second organic protection layer, which is modelled as an RC network 72 in FIG. 10, is formed as an upper layer (the layer 60 in FIG. 9). Both layers are tested for their time-delay in response to a pulse input from a generator 74, these time delays being detected by respective timers 76, 78, which receive input signals from respective signal detectors 80, 82. In addition a memory 84 has stored therein the value of a reference time delay. So far the testing circuit for each layer in FIG. 10 resembles that shown in FIG. 2 for testing the single layer shown in FIG. 1. An additional component in FIG. 10, however, is a processor circuit 86, which takes as its inputs the outputs of the timers 76 and 78...
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