Method of forming titanium film by CVD
a technology of titanium film and cvd, which is applied in the direction of coating, chemical vapor deposition coating, coating, etc., can solve the problems of reaction deterioration of step coverage, and achieve the effect of increasing the selectivity of silicon-to-insulating film and avoiding deterioration of tisix layer morphology
Inactive Publication Date: 2009-03-19
TADA KUNIHIRO +1
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Benefits of technology
The present invention provides a method for forming a titanium film on a silicon base by chemical vapor deposition in holes formed in an insulating film. The method includes heating the substrate, supplying processing gases including TiCl4 gas, a reduction gas, Ar gas, and SiH4 gas, and producing a plasma in the film forming chamber to deposit a titanium film. The method also includes adjusting the flow rates of the processing gases to achieve a silicon-to-insulating film selectivity of not less than one, and using specific gas mixtures to prevent deterioration of the morphology of the TiSix layer. Additionally, the present invention provides cleaning methods for removing titanium films or other films formed on the substrate.
Problems solved by technology
However, since SiH4 gas is a reducing gas, TiSix is produced by the interaction of SiH4 gas and TiCl4 gas and such a reaction deteriorates the step coverage.
Method used
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[0038]Referring to FIG. 1, a film forming system for carrying out a method of forming a titanium (Ti) film by CVD in a preferred embodiment of the present invention has a substantially cylindrical vessel 1 defining an airtight film forming chamber, a susceptor 2 for supporting a silicon (Si) wafer or substrate W, i.e., an objected to be processed, in a horizontal attitude thereon, and a cylindrical support member 3 supporting the susceptor 2 for vertical movement. A heating element 4 is embedded in the susceptor 2. Power is supplied by a power source, not shown, to the heating element 4 to heat a silicon (Si) wafer W supported on the susceptor 2 at a predetermined temperature.
[0039]A shower head 10 is disposed on the upper wall of the vessel 1 so as to face a Si wafer W supported on the susceptor 2. The shower head 10 has a lower wall provided with a plurality of gas discharge holes 10a and facing a Si wafer W supported on the susceptor 2, a space 11, a perforated diffusing wall 12 ...
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Abstract
A Ti film is formed by CVD in holes formed in an insulating film formed on a Si substrate or on a Si film formed on a Si substrate by a method according to the present invention. The method includes the steps of: loading a Si substrate into a film forming chamber; evacuating the chamber at a predetermined vacuum; supplying TiCl4 gas, H2 gas, Ar gas and SiH4 gas into the film forming chamber; and producing a plasma in the film forming chamber to deposit a Ti film in the holes formed in the insulating film. The Si substrate is heated at 500° C. or below during the deposition of the Ti film. The flow rate of the SiH4 gas is from 30 to 70% of the flow rate of the TiCl4 gas. This method enables formation of a Ti film on a Si base at positions of holes in an insulating layer, with a good morphology of the interface between the Si base and the Ti film and with a good step coverage.
Description
CROSS-REFERENCE TO RELATED APPLICATION[0001]This is a continuation-in-part application of our application Ser. No. 09 / 713,008 filed Nov. 16, 2000, which is a continuation-in-part application of our application Ser. No. 09 / 216,938 filed Dec. 21, 1998.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a method of forming a titanium (Ti) film to be used as a contact metal film or an adhesion layer for a semiconductor device by a chemical vapor deposition (CVD) process.[0004]2. Description of the Related Art[0005]Recently, most semiconductor integrated circuits are fabricated in a circuit configuration of a multilevel structure to cope with market demand for high-density and large-scale integration. Accordingly, techniques for filling contact holes for the electrical connection of semiconductor devices formed in a lower layer to wiring lines formed in upper wiring layers, and via holes for the electrical connection of wiring lines in differe...
Claims
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IPC IPC(8): C23C16/54C25F1/00C23C16/14C23C16/04C23C16/08H01L21/28H01L21/285H01L21/31H01L21/768
CPCC23C16/045H01L21/76843C23C16/08
Inventor TADA, KUNIHIROOTSUKI, HAYASHI
Owner TADA KUNIHIRO