Semiconductor packages and methods of manufacturing the same

Abstract

Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 2008-0006703, filed on Jan. 22, 2008, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]Exemplary embodiments disclosed herein relate to semiconductor packages and methods of manufacturing the same, and more particularly, to semiconductor packages including two kinds of pads to which different kinds of external terminals are connected, and methods of manufacturing the same.[0004]2. Description of the Related Art[0005]A trend in the recent electronics industry is to manufacture a semiconductor device economically which is small, light, speedy, highly reliable, and highly efficient. One of the techniques which can manufacture the recently innovated semiconductor devices are semiconductor packaging techniques.[0006]A recent application device of an i...

AI Technical Summary

Problems solved by technology

A recent application device of an integrated circuit requires a number of I / O pins, but a number of I / O pins causes many problems with relation to a conventional wire bonding package.

As the number of I / O pins increases, there is a limitation of a minimum bond pitch that occurs by a limited size of a substrate.

However, some characteristics of materials used in each of the techniques are unfavorable to work with.

Materials suitable for use as solder bumps have poor characteristics of mechanical adhesion.

Thus, a material like copper, for example, is a good soldering material but is not well selected for the use of a wire bonding, One reason it that copper easily forms an oxide layer that provides a bad bonding characteristic.

However, corrosive agents for removing the oxide layer are very strong, so that aluminum disposed under an oxide layer is also corroded.

However, gold disposed on a solder bump pad is easily diffused into adjacent copper or adjacent solder and forms not only a void but also forms an undesired intermetallic compound that is vulnerable to an impact.

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