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Test circuit and test method for power switch

a test circuit and power switch technology, applied in the direction of electronic circuit testing, measurement devices, instruments, etc., can solve the problems of increasing the complexity of the application of portable devices, the percentage of standby power consumption, and the total system standby power consumption, etc., and achieve the effect of low cos

Inactive Publication Date: 2010-02-25
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009]The invention provides a low cost test circuitry and methodology for on-chip testing on-chip header type power switches, footer type power switches and hybrid type power switches.
[0010]The invention provides a test circuitry and method for improving test coverage of power switch design.

Problems solved by technology

Due to the dramatic increase of application complexity of portable devices, they need to use advanced process, for example, 45 nm, to implement as many features as possible.
Therefore, as the number of circuit devices increases, the percentage of standby power consumption due to the above-mentioned leakage is increasing, and is becoming the dominant portion of the total system standby power consumption.
The use of higher threshold voltage devices decreases the off-state leakage and gate tunneling effects that otherwise increase power consumption when the repeaters are not switching.
However, there is no good test method to test on-chip power switches in CP (chip probe) or FT (final test) stage.

Method used

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  • Test circuit and test method for power switch
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  • Test circuit and test method for power switch

Examples

Experimental program
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first embodiment

[0024]FIG. 2 shows a test circuit for testing a header type MTCMOS power switch 200 (PMOS) in a single power domain, according to a first embodiment of the invention. As shown in FIG. 2, the core logic 210 includes logic circuitry and further the decoupling capacitor (decap) 231. In other words, the decap 231 is an equivalent decoupling capacitance of the core logic 210. For simplicity, the decap 231 is shown as being connected parallel with the core logic 210. The test circuit includes a discharge circuit 220, a flip-flop 233, a MUX 235 and a test result isolation element 237.

[0025]The discharge circuit 220 is used for discharging the decap 231. The discharge speed of the decap 231 will affect the test speed of the power switch. Faster the discharge speed, faster the test speed.

[0026]The logic H discharge signal DSG and the logic H output signal from the MUX 235 will turn on the MOS transistor 222 and accordingly the decap 231 is discharged by the turned-ON MOS transistor 222.

[0027...

second embodiment

[0037]FIG. 4 shows a test circuit for testing a footer type MTCMOS power switch 400 (NMOS) in a single power domain, according to a second embodiment of the invention. The test circuit includes a pre-charge circuit 420, a flip-flop 433, a MUX 435 and a test result isolation element 437.

[0038]The pre-charge circuit 420 is used for pre-charging the decap 431. The pre-charge speed of the decap 431 will affect the test speed of the power switch. Faster the pre-charge speed, faster the test speed.

[0039]The pre-charge circuit 420 includes a logic circuit 421 and a MOS transistor 422. The logic circuit 421, for example an OR logic gate, receives a pre-charge signal PG and an output signal from the MUX 435. The MOS transistor 422 has a source terminal coupled to the power supply VCC, a drain terminal coupled to the decap 431 and a gate terminal coupled to an output from the logic circuit 421.

[0040]Both the logic L pre-charge signal PG and the logic L output signal from the MUX 435 will turn...

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PUM

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Abstract

For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of Invention[0002]The present invention relates to test circuits and test method for power switches, and more particularly to on-chip test circuits and test method for testing on-chip power switches.[0003]2. Description of Related Art[0004]Low power electronic systems incorporating circuit elements are increasingly prevalent, as SOC (system on chip) is widely used in many portable devices, for example, personal digital assistants (PDAs), digital still camera (DSC) and other electronic appliances.[0005]Due to the dramatic increase of application complexity of portable devices, they need to use advanced process, for example, 45 nm, to implement as many features as possible. As the process progresses, the leakage current of circuit devices, namely PMOS and NMOS, increases, rapidly. In most portable devices, they need to reduce the standby current to extend battery life. The standby mode power consumption is now determined by the quiescent “off-...

Claims

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Application Information

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IPC IPC(8): G01R31/302
CPCG01R31/3277G01R31/3187
Inventor CHEN, WANG-CHINSU, CHUN-SUNG
Owner FARADAY TECH CORP