Multilayer chip capacitor

Abstract

A multilayer chip capacitor includes: a capacitor body having a plurality of dielectric layers laminated therein and comprising first and second capacitor units; and first to fourth external electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the first and second external electrodes, and having different polarities, each pair of first and second internal electrodes being laminated one or more times to discriminate a plurality of capacitors with a certain capacitance, the second capacitor unit comprises third and fourth internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the third and fourth external electrodes, and having the same polarities as those of the first and second internal electrodes, each pair of third and fourth internal electrodes being laminated one or more times to discriminate one or more capacitors each with a certain capacitance, and at least three capacitors included in the first and second capacitor units have different capacitances or resonance frequencies.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the priority of Korean Patent Application No. 2008-0099742 filed on Oct. 10, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a multilayer chip capacitor and, more particularly, to a multilayer chip capacitor that can be suitably used as a decoupling capacitor of a power distribution network of a micro-processor unit (MPU) and reduce, as a single capacitor, impedance of the power distribution network to a target impedance or less in a broad frequency range of hundreds of kHz to hundreds of MHz.[0004]2. Description of the Related Art[0005]Designing a power distribution network (PDN) of a microprocessor unit (MPU) is increasingly difficult as the MPU becomes faster in speed and more integrated. In particular, a decrease in a power voltage and an increase in curr...

AI Technical Summary

Benefits of technology

The solution effectively reduces the number of decoupling capacitors needed, minimizing mounting costs and space while maintaining target impedance across a broad frequency range, and prevents capacitance degradation by using capacitor units with different capacitances.

Problems solved by technology

Designing a power distribution network (PDN) of a microprocessor unit (MPU) is increasingly difficult as the MPU becomes faster in speed and more integrated.

In particular, a decrease in a power voltage and an increase in current consumption of the MPU resulting from the integration of the MPU lead to a gradual lowering of a target impedance (Ztarget) as represented by equation shown below:

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