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RF chip test method

Active Publication Date: 2010-05-20
KING YUAN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]Accordingly, the present invention has been made in order to meet needs including that described above, and it is an object of the present invention to provide an RF chip test method responsive to this need. By using the RF chip test method, use of RF relays for testing the contact condition between RF pins and the chip socket can be eliminated.
[0014]The RF chip test method of the present invention is capable of testing the contact condition between RF pins and the chip socket without RF relays. The test result of the RF chip is stable, and the efficiency of the test process is also increased.

Problems solved by technology

However, there are some disadvantages associated with the RF relays.
The RF relays have to use the space of the test board 120, the cost of the RF relay is high, the working life of the RF relay is short, and it is necessary to change RF relays frequently in mass production contexts.
Therefore, the cost of the RF chip test is increased.
As a consequence of RF relays increasing the high frequency parasitic capacitance and parasitic inductance of the test circuit of the test board 120, chip test results are adversely affected by high frequency parasitic capacitance and parasitic inductance.
Therefore, the test result of the RF chip is not stable.
Therefore, the efficiency of the RF chip test process is low.

Method used

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Embodiment Construction

[0024]The detailed description of the present invention will be discussed in the following embodiments, which are not intended to limit the scope of the present invention and which can be adapted for other applications. While the drawings are illustrated in detail, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed with the exception of contexts expressly restricting the amount of the components.

[0025]FIG. 2 shows a flow diagram of an RF chip test method 300 in accordance with a preferred embodiment of the present invention. The RF chip test method 300 includes the following steps.

[0026]First, with reference to FIG. 1, the performance of step 310 comprises disposing a chip 50 within a chip socket 110. The chip 50 has at least one non-RF pin 51 and at least one RF pin 52. The chip socket 110 is disposed on a test board 120. The test board 120 has at least one test circuit. The chip socket 110 has a plurality of conductive elemen...

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PUM

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Abstract

An RF chip test method is disclosed. The RF chip test method includes disposing an RF chip within a chip socket, with the RF chip having at least one RF pin and at least one non-RF pin, the chip socket having conductive elements, and the conductive elements contacting the RF pin and the non-RF pin; connecting the non-RF pin to a ground end and connecting the RF pin to an RF measuring instrument; measuring a S11 parameter of the RF pin using the RF measuring instrument; and comparing the S11 parameter with an allowable range so as to judge the contact condition between the RF pin and the conductive element.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to a chip test method, and more particularly to an RF chip test method.[0003]2. Description of the Prior Art[0004]Chip tests are typically performed during semiconductor chip production processes to ensure the quality of electrical characteristics of the semiconductor chips being fabricated. FIG. 1 is a schematic diagram corresponding to a prior-art chip test process. A chip 50 is disposed within a chip socket 110. The chip 50 has at least one non-RF pin 51 and at least one RF pin 52. The chip socket 110 is disposed on a test board 120. The test board 120 has at least one test circuit. The chip socket 110 has a plurality of conductive elements 130. The press mechanism 70 moves downward to make the conductive elements 130 contact the non-RF pin 51 and the RF 52 pin tightly.[0005]Generally, when performing the chip test process of the chip 50, a DC open / short test will be performed ...

Claims

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Application Information

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IPC IPC(8): G01R31/02
CPCG01R27/04G01R31/2822G01R31/043G01R31/68
Inventor KO, HSUAN-CHUNGCHEN, HSIU-JU
Owner KING YUAN ELECTRONICS