Pipeline time-to-digital converter

Abstract

A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 98134319, filed Oct. 9, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.BACKGROUND[0002]1. Technical Field[0003]The present disclosure relates to a time-to-digital converter (TDC). More particularly, the present disclosure relates to a pipeline TDC.[0004]2. Description of Related Art[0005]A time-to-digital converter (TDC) is one of important techniques in development of integrated circuits, and the TDC is widely used in communication chips, biomedical chips and measurement chips. For example, in a digital phase-locked loop (DPLL) of the communication chip, a TDC with a high resolution is used to reduce in-band phase noise of the loop. If the phase noise is required to be less than 100 dB c / Hz, the resolution is required to be 6 ps. However, design of a high resolution TDC is ...

AI Technical Summary

Benefits of technology

[0011]Consistent with the embodiment, there is provided a pipeline time-to-digital converter (TDC), which is a high resolution TDC designed based on a simple, flexible and effective circuit design structure. According to a pipeline processing, a resolution and a dynamic-range can be both considered, and processing of an accurate time amplification gain required by a time amplifier is unnecessary, so that design and usage of the pipeline TDC can be more efficiency.

Problems solved by technology

However, design of a high resolution TDC is a great challenge.

A resolution of such structure is limited by the delay buffers, and highly relates to a semiconductor process, which can only provide a resolution of 20 ps in a CMOS 90 nm process.

Such structure requires a rather complex calibration circuit to calibrate the time amplifier, and a main problem thereof is that an accurate time amplification gain of time cannot be obtained according to a feedback approach as that does of a voltage, so that a non-ideal effect of the time amplifier is an intractable problem.

However, such structure requires rather high oscillation frequency and consumes rather great power (about 10 times) to obtain a relatively high resolution (for example, 1 ps).

However, a shortage of such structure is that if the dynamic-range of the circuit operation is increased, i.e. a frequency of the high-speed clock is decreased, a plurality of the high-speed clocks cannot be used to generate the difference, so that the resolution is decreased.

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