Duty cycle correction circuit

Abstract

A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a duty cycle correction circuit for providing a clock signal with a half duty cycle or a one-Nth duty cycle.2. Description of the Related ArtGenerally, a delay locked loop (DLL) is used in a synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), to perform synchronization between an internal clock signal and an external clock signal of the synchronous semiconductor memory device. A DDR SDRAM employs a rising edge and a falling edge of a clock signal to process data so as to increase the operation speed of data. As the operational speed of the DDR SDRAM is increased, performance of the DDR SDRAM is greatly affected by the DLL. Therefore, since design margin decreases with an increase of duty error, having a correct duty cycle of the internal clock is important. Reliable data transmission is achieved when the duty cycle is equivalent t...

AI Technical Summary

Benefits of technology

The solution effectively corrects duty cycles with reduced power consumption and silicon area, improving operation efficiency and maintaining sufficient design margin for reliable data transmission in semiconductor memory devices.

Problems solved by technology

As the operational speed of the DDR SDRAM is increased, performance of the DDR SDRAM is greatly affected by the DLL.

Therefore, since design margin decreases with an increase of duty error, having a correct duty cycle of the internal clock is important.

However, the phase mixer comprises a plurality of drivers to implement pull-up and pull-down functions, and therefore consumes a large amount of power and requires a large silicon area.

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