Thin film transistor array panel and method for manufacturing the same including forming a temperature dependent gate insulating layer
a technology of thin film transistors and array panels, which is applied in the direction of electrical equipment, semiconductor devices, instruments, etc., can solve the problems of degrading reliability, increasing the length of gate lines and data lines, and concomitant increase in wiring resistance, so as to achieve the effect of eliminating or reducing the agglomeration problem
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embodiment 1
[0029]First, a TFT array panel according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. FIG. 1 is a layout view of a TFT array panel according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of the TFT array panel shown in FIG. 1 taken along the line II-II and the line III-III, respectively. A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of a material such as transparent glass or plastic.
[0030]The gate lines 121 for transmitting gate signals extend substantially in a transverse direction. Each of the gate lines 121 includes a plurality of gate electrodes 124 that protrude downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driver (not shown) for generating the gate signals may be mounted on a flexible printed circuit film (not shown) attached to the...
embodiment 2
[0063]Now, a TFT array panel according to another embodiment of the present invention will be described with reference to FIGS. 16 to 18. FIG. 16 is a layout view of a TFT array panel according to an embodiment of the present invention, and FIGS. 17 and 18 are sectional views of the TFT array panel shown in FIG. 16 taken along the line XVII-XVII and the line XVIII-XVIII. The structure of the TFT array panel according to the present embodiment is substantially the same as that illustrated in FIGS. 1 to 3.
[0064]A plurality of gate lines 121 having gate electrodes 124 and end portions 129 and a plurality of storage electrode lines 131 having storage electrodes 133a and 133b are formed on a substrate 110, and a gate insulating layer 140, a plurality of semiconductor stripes 151 having projections 154, a plurality of ohmic contact stripes 161 having projections 163, and a plurality of ohmic contact islands 165 are sequentially formed thereon. A plurality of data lines 171 having source e...
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