Thermal warp compensation IC package

Inactive Publication Date: 2012-04-05
ALCATEL LUCENT SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In general, ICs and their packages have been becoming more complex over time, with the result that their power, speed and their size has been increasing.
With increased size and complexity also arise an increased number of connections from the integrated circuit to the larger electronics assembly of which it is a part.
One disadvantage of BGAs however, is the requirement for flatness during processing.
Working against this requirement, however, is the difference in thermal coefficient of expansion which exists between the substrate upon which the solder balls are mounted, and the silicon integrated circuit mounted upon the substrate.
The differences in the thermal coefficient of expansion lead to warpage of the BGA package as a whole.
This warpage, which for the purposes of this specification refers to a bending or twist or general lack of flatness in the overall integrated circuit package, including in particular the plane formed by the solder joint locations, can cause a variety of problems.
The problem of warpage is exacerbated by larger package sizes, and by elevated processing temperatures.
As trends in integrated circuit complexity are consistently in the direction of larger package sizes, and as production changes in the direction of lead free solders yield higher processing temperatures, the problem of integrated circuit warpage is a pressing one.
However, these stiffener flat plates suffer from the disadvantage that they themselves are entirely flat, and thus, have a somewhat limited resistance to warping due to temperature change or torsion or bending forces.
In order to make a flat plate strong enough to provide desirable resistance to warping in the overall IC package, it can be necessary to make the stiffening plate undesirably thick.
It is undesirable for the stiffening plate, which rests on top of the IC, to be too thick because the thick stiffening plate, on top of and added to the IC thickness, causes the entire assembled IC package to be thick, thus potentially limiting IC packaging placement options and / or increasing printed circuit card to printed circuit card separation in the final system assembly.
Further, the added stiffener thickness increases the IC die-to-lid spacing, thereby creating a larger separation that needs to be filled with thermal interface material, the longer thermal path ultimately impeding thermal dissipation from the IC.
Moreover, because of the stiffener's entirely flat cross-sectional profile, increased stiffness is achieved inefficiently though the increase of the overall volume of material, thus adding additional cost and weight to the final IC package.

Method used

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Embodiment Construction

[0036]Referring now to the drawings, in which like numerals refer to like components or steps, there are disclosed broad aspects of various exemplary embodiments.

[0037]Many embodiments relate to a warpage reducing element that can be attached to an integrated circuit (IC) package. As used throughout this document, the terms IC (integrated circuit) and IC packaging are used interchangeably to make reference to the overall component assembly, which is also commonly referred to as the IC package. Examples of IC packages include for example TSOPS, QFPs, SOIC, BGA, CCGA, etc. It is noted that for packages containing above approximately 400 connections, IC packaging almost exclusively take on the form of Area Array style packaging, which itself can include various subtypes, such as for example Column Grid Arrays (CCGA), Pin Grid Arrays (PGA), and Ball Grid Arrays (BGA). The stiffener solutions that are described herein are applicable to such Area Array devices, including for example BGAs....

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Abstract

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

Description

FIELD OF THE INVENTION[0001]The invention relates to warping of integrated circuit (IC) packages during manufacturing processing and is particularly concerned with providing a means for generally neutralizing the warpage by use of a counter-warping element.BACKGROUND OF THE INVENTION[0002]A wide variety of semiconductor packages having integrated circuits (IC) are used in industry. In general, ICs and their packages have been becoming more complex over time, with the result that their power, speed and their size has been increasing. With increased size and complexity also arise an increased number of connections from the integrated circuit to the larger electronics assembly of which it is a part. Historically, pin counts of Very Large Scale Integrated (VLSI) circuits exceeded the limits for dual in-line packaging (DIPs), leading to development of the Pin Grid Array (PGA). In the PGA the inputs and outputs of the integrated circuit are connected to an integrated circuit package in wh...

Claims

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Application Information

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IPC IPC(8): H05K7/00H01L21/50
CPCH01L23/49816H01L23/49822H01L27/04H01L2924/3511H01L21/58H01L2924/15311H01L24/80H01L2924/14H01L2924/00
InventorBROWN, PAUL JAMESCHAN, ALEX L.
OwnerALCATEL LUCENT SAS